HDMI/DVI Switch. AD8197B Datasheet

AD8197B Switch. Datasheet pdf. Equivalent


Analog Devices AD8197B
4:1 HDMI/DVI Switch with Equalization
AD8197B
FEATURES
4 inputs, 1 output HDMI/DVI links
Enables HDMI 1.3-compliant receiver
Pin-to-pin compatible with the AD8197A
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
www.DataSheet4U.cEoqmualized inputs allow use of long HDMI cables
(20 meters at 2.25 Gbps)
Fully buffered unidirectional inputs/outputs
Per input switchable, 50 Ω on-chip terminations
Switchable output 50 Ω on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)
4 auxiliary channels per link
Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
Allows switching of DDC bus and 2 additional signals
Output disable feature
Reduced power dissipation
Removable output termination
Allows building of larger arrays
Two AD8197Bs support HDMI/DVI dual link
Standards compatible: HDMI receiver, HDCP, DVI
Serial (I2C slave) and parallel control interface
100-lead, 14 mm × 14 mm LQFP, Pb-free package
APPLICATIONS
Multiple input displays
Projectors
A/V receivers
Set-top boxes
Advanced television (HDTV) sets
TYPICAL APPLICATION
MEDIA CENTER
HDTV SET
GAME CONSOLE
SET-TOP BOX
HDMI
RECEIVER
AD8197B
DVD PLAYER
04:20
Figure 1. Typical HDTV Application
FUNCTIONAL BLOCK DIAGRAM
PARALLEL
SERIAL
2
2
I2C_SDA
I2C_SCL
I2C_ADDR[2:0]
VTTI
3
CONFIG
INTERFACE
RESET
CONTROL
LOGIC
AD8197B
AVCC
DVCC
AMUXVCC
AVEE
DVEE
IP_A[3:0] +
IN_A[3:0]
IP_B[3:0] +
IN_B[3:0]
IP_C[3:0]
+–
IN_C[3:0]
IP_D[3:0] +
IN_D[3:0]
4
4
4
4
4
4 EQ
4
4
SWITCH
CORE
PE
4
4
HIGH SPEED BUFFERED
VTTO
+ OP[3:0]
ON[3:0]
VTTI
AUX_A[3:0]
AUX_B[3:0]
AUX_C[3:0]
AUX_D[3:0]
4
4
4
SWITCH
CORE
4
4
LOW SPEED UNBUFFERED
BIDIRECTIONAL
AUX_COM[3:0]
Figure 2.
GENERAL DESCRIPTION
The AD8197B is an HDMI™/DVI switch featuring equalized
TMDS® inputs and pre-emphasized TMDS outputs, ideal for
systems with long cable runs. The AD8197B offers individual
control of the on/off state of the TMDS input termination
resistors via I2C® control. Outputs can be set to a high
impedance state to reduce the power dissipation and/or to allow
the construction of larger arrays using the wire-OR technique.
The AD8197B is provided in a 100-lead LQFP, Pb-free, surface-
mount package, specified to operate over the −40°C to +85°C
temperature range.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
2. Input cable equalizer enables use of long cables at the input
(more than 20 meters of 24 AWG cable at 2.25 Gbps).
3. Auxiliary switch routes a DDC bus and two additional signals
for a single-chip, HDMI 1.3 receive-compliant solution.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.


AD8197B Datasheet
Recommendation AD8197B Datasheet
Part AD8197B
Description 4:1 HDMI/DVI Switch
Feature AD8197B; 4:1 HDMI/DVI Switch with Equalization AD8197B FEATURES 4 inputs, 1 output HDMI/DVI links Enables HDM.
Manufacture Analog Devices
Datasheet
Download AD8197B Datasheet




Analog Devices AD8197B
AD8197B
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Application........................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
www.DataAShbesoeltu4Ute.cMomaximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 13
Introduction ................................................................................ 13
Input Channels............................................................................ 13
Output Channels ........................................................................ 13
Auxiliary Switch.......................................................................... 14
Serial Control Interface.................................................................. 15
Reset ............................................................................................. 15
Write Procedure.......................................................................... 15
Read Procedure........................................................................... 16
REVISION HISTORY
1/08—Revision 0: Initial Version
Switching/Update Delay............................................................ 16
Parallel Control Interface .............................................................. 17
Serial Interface Configuration Registers ..................................... 18
High Speed Device Modes Register......................................... 19
Auxiliary Device Modes Register............................................. 19
Receiver Settings Register ......................................................... 19
Input Termination Select Register 1 and Register 2 .............. 19
Receive Equalizer Register 1 and Register 2 ........................... 19
Transmitter Settings Register.................................................... 20
Parallel Interface Configuration Registers .................................. 21
High Speed Device Modes Register......................................... 22
Auxiliary Device Modes Register............................................. 22
Input Termination Resistor Control Register 1
and Register 2.............................................................................. 22
Receive Equalizer Register 1 and Register 2 ........................... 22
Transmitter Settings Register.................................................... 22
Application Information................................................................ 23
Pinout........................................................................................... 23
Cable Lengths and Equalization............................................... 23
PCB Layout Guidelines.............................................................. 24
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. 0 | Page 2 of 28



Analog Devices AD8197B
AD8197B
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Bit Error Rate (BER)
Added Deterministic Jitter
Added Random Jitter
www.DataSheet4UD.icffoemrential Intrapair Skew
Differential Interpair Skew1
EQUALIZATION PERFORMANCE
Receiver (Highest Setting)2
Transmitter (Highest Setting)3
INPUT CHARACTERISTICS
Input Voltage Swing
Input Common-Mode Voltage (VICM)
OUTPUT CHARACTERISTICS
High Voltage Level
Low Voltage Level
Rise/Fall Time (20% to 80%)
INPUT TERMINATION
Resistance
AUXILIARY CHANNELS
On Resistance, RAUX
On Capacitance, CAUX
Input/Output Voltage Range
POWER SUPPLY
AVCC
QUIESCENT CURRENT
AVCC
VTTI
VTTO
DVCC
AMUXVCC
POWER DISSIPATION
TIMING CHARACTERISTICS
Switching/Update Delay
RESET Pulse Width
Conditions/Comments
NRZ
PRBS 223 − 1
DR ≤ 2.25 Gbps, PRBS 27 − 1, EQ = 12 dB
At output
At output
Boost frequency = 825 MHz
Boost frequency = 825 MHz
Differential
Single-ended high speed channel
Single-ended high speed channel
Single-ended
Min
2.25
150
AVCC − 800
AVCC − 10
AVCC − 600
75
DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz
DVEE
Operating range
3
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
Input termination on4
Output termination on, no pre-emphasis
Output termination on, maximum pre-emphasis
30
52
95
5
35
72
3.2
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
High speed switching register: HS_CH
All other configuration registers
115
384
704
50
Typ Max
Unit
10−9
25
1
1
40
Gbps
ps (p-p)
ps (rms)
ps
ps
12 dB
6 dB
1200
AVCC
mV
mV
AVCC + 10 mV
AVCC − 400 mV
135 200
ps
50 Ω
100
8
AMUXVCC
Ω
pF
V
3.3 3.6
V
40 44
60 66
110 122
40 54
40 46
80 90
78
0.01 0.1
mA
mA
mA
mA
mA
mA
mA
mA
271 361
574 671
910 1050
mW
mW
mW
200 ms
1.5 ms
ns
Rev. 0 | Page 3 of 28





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