DC/DC Converters. AN703 Datasheet

AN703 Converters. Datasheet pdf. Equivalent

AN703 Datasheet
Recommendation AN703 Datasheet
Part AN703
Description Designing DC/DC Converters
Feature AN703; AN703 Vishay Siliconix AN703 www.DataSheet4U.com Designing DC/DC Converters with the Si9110 Switchm.
Manufacture Vishay Intertechnology
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Vishay Intertechnology AN703
Vishay Siliconix
Designing DC/DC Converters with the
Si9110 Switchmode Controller
In distributed power systems and battery-powered equipment,
the advantages of MOS over bipolar technology for pulse-
width modulation (PWM) controllers are significant. First, by
using a BiC/DMOS power IC process, a high-voltage DMOS
transistor can be integrated with a CMOS PWM controller to
serve as a pre-regulator stage. This reduces the number of
external components by permitting the power controller IC to
interface directly to the power bus.
The second advantage of MOS is speed. Bipolar PWM
controllers can be made fast, but only with a significant
increase in supply current. Logic gate delays of 5 ns are
readily achievable using 5-µm CMOS, comparator
propagation delays are in the 50- to 100-ns range, and the
supply current is maintained below 1 mA.
How does speed translate into power supply performance?
The answer is first in reliability and second in power density. If
the delay time is long between the sensing of an overcurrent
condition in the power switch and the turn-off of the switch,
then the peak and RMS current values reach excessive levels
and the switch fails. A well-designed power supply should
tolerate a continuous short circuit on any output. To
accomplish this with a slow controller IC, extra protection
circuitry or an oversized switching transistor and heatsink are
required. But that costs money.
Power supply density (often expressed as output power in
watts divided by volume in cubic inches) has steadily been
increasing over the past 5 to 10 years. By increasing the
switching frequency, the size of magnetics and filter
capacitors has been reduced, allowing smaller and less
expensive power supplies to be built. To increase the
switching frequency to the 100- to 500-kHz range and still
achieve high reliability requires that the current limit delay time
be kept under approximately 100 ns.
The first BiC/DMOS switchmode controller IC to meet these
requirements is the Si9110. Its 500-kHz rating for maximum
switching frequency is fully usable, thanks to the high-speed
current limit comparator and the efficient output driver stage,
which essentially eliminates the shoot-through current found
in bipolar totem-pole circuits. The DMOS transistor in the
input pre-regulator has a breakdown voltage rating of 120 V,
which provides ample headroom for operation from typical bus
voltages in distributed power systems (where 12, 24, 48, and
60 V are frequently encountered).
The appeal of such distributed power processing systems is in
their flexibility and reliability. By bussing power at a higher
voltage, smaller conductors can be used, as well as fewer
connector pins to get the power to where it is needed-on the
circuit card. An on-card power supply can then provide the
voltages needed in that part of the system. The power bus
voltage is usually chosen to be low enough to eliminate the
need for safety agency approvals, and a battery can be
connected through a diode to the power bus to provide
emergency back-up. The distributed power approach is
employed in telecom systems, large minicomputers, and in
other applications where reliability is a primary concern.
To illustrate some of the performance capabilities of this BiC/
DMOS switchmode controller IC, a 15-W forward converter
design is presented. The converter provides +5-V and ±12-V
outputs from a 9- to 36-V input range. This permits the power
supply to operate from 12-V or 24-V batteries, or from a 28-V
aircraft power source. Before describing the forward converter
example, it is instructive to review the operation of each of the
Si9110 switchmode controller’s functional blocks.
A BiC/DMOS power integrated circuit process is used to
integrate a high-voltage (120-V rated) lateral DMOS transistor
with the CMOS PWM controller. By using an ion implant to
shift the gate threshold to a negative value, as shown in
Figure 1, the transistor is made to operate as a depletion-
mode device. This eliminates the need for a pull-up voltage
above VIN to turn the device on, and an amplifier and voltage
reference can be used to implement a linear regulator, as
shown in Figure 2. The CMOS circuitry is thus protected from
transients which appear on the input power bus.
FIGURE 1. Depletion-Mode MOSFET Characteristics
FIGURE 2. Pre-regulator/Start-up Circuit
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wInwswo.DmaetaaSphpeelict4aUti.oconms it is useful to turn off the pre-regulator
after start-up. This is easily accomplished by using an
auxiliary winding on the transformer to develop a bootstrap
supply voltage. After the converter starts, its own output feeds
10 to 12 V to pin 6 (VCC), and the amplifier pulls the gate of
the MOSFET to the -VIN rail. Thus, VGS = -VCC, and the
device is turned off.
A ring of inverters and internal MOS capacitors forms the
oscillator circuit, as shown in Figure 3. This circuit requires
only a resistor (no external capacitor) to program the
frequency. The internal capacitance is charged towards VCC
through ROSC. When the capacitor voltage reaches VCC/2, the
CMOS logic threshold, inverter INV1 changes state (from high
to low), and the INV2 output goes from a low to a high output.
The capacitor, C2, provides positive feedback to ensure stable
operation without frequency jitter. It also causes the “bump” at
the end of the ramp until INV2 can turn on the discharge
switch, Q1, to terminate the cycle.
Oscillator synchronization is achieved by prematurely
terminating each clock cycle using a positive going pulse
capacitively coupled onto the oscillator ramp voltage. The
pulse forces INV1 to change states, Q1 discharges C = C1 +
C2, and the cycle repeats. An internal flip-flop blanks out the
output during every other clock cycle, so the switch duty ratio
is limited to a maximum of 50%. Therefore, the oscillator
frequency and SYNC pulse repetition rate must be set at two
times the switching frequency, fs.
Error Amplifier
The bias resistor connected from pin 1 (BIAS) to pin 5 (-VIN)
programs the current sources in the analog portion of the
current-mode controller - including the error amplifier, the
current-mode and current-limit comparators, and the voltage
reference. The Si9110 data sheet guarantees the
performance of these functions at one value of bias current -
15 µA. It is possible to change the performance
characteristics of these functions by changing the bias
current, and Appendix A explains how this is accomplished.
The error amplifier circuit employs PMOS transistors in a
differential input stage to achieve a high input impedance of
40 Mtypically (2 Mminimum). This input impedance,
combined with a 1-ksmall-signal output impedance, enables
the amplifier to be used with feedback compensation, unlike
transconductance error amplifiers. The amplifier can source
2 mA and sink 0.140 mA, as can be seen from the output
stage equivalent circuit in Figure 4. Yes, an NPN transistor is
used here. Most of the PWM controller is CMOS, but the
process allows the flexibility of using bipolar devices where
they are advantageous.
The error amplifier is unity gain stable with a typical bandwidth
of 1 MHz and 60° phase margin. Bias current values of from
5 µA to 50 µA have been tested, and the error amplifier does
remain stable over this range. Actually, the bandwidth and
phase margin increase somewhat as IBIAS is increased above
15 µA. Higher bias currents may, therefore, be useful when
compensating higher frequency converters (above 250 kHz).
FIGURE 3. Si9110 Oscillator Circuit Operation
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FIGURE 4. Error Amplifier Output Stage
FIGURE 5. Current-limit Comparator Delay
(Equivalent Circuit Model)
Voltage Reference
A buried zener with merged temperature compensating diode
(patent pending) is used to achieve stability of 0.25 mV/°C.
The Si9110 voltage reference is trimmed to 4 V plus or minus
1% with a bias current of 15 µA. This voltage varies by about
1% as IBIAS is varied from 5 to 50 µA. If 1% reference
accuracy must be guaranteed, IBIAS should be set at 15 µA.
For circuits employing an external reference on the secondary
side, such as those used with optically coupled feedback, the
Si9111 is an economical approach. Its voltage reference
provides a dc bias point at the input to the error amplifier
where its 10% accuracy is more than sufficient. The reference
accuracy is the only difference between the Si9110 and
The delay time of the current-limit and current-mode
comparators can be modeled as a current source charging an
internal nodal capacitance, as shown in Figure 5. The current-
mode comparator is intentionally made to be four times slower
than the current-limit comparator. In many circuits, this
permits the elimination of the RC filter in the current-sense
circuit, which is used to prevent false trips by the leading edge
current spike. After one of the comparator outputs goes high,
there is an additional 20 ns of gate propagation delay before
the output driver can begin switching.
The total current-limit delay to output versus IBIAS is shown in
Figure 6 for VCC equal to 8.5 V. The delay time is 180 ns for
IBIAS = 5 µA, but decreases to 50 ns for IBIAS = 30 µA. As
operating frequency is increased, IBIAS may be increased to
speed up the current limiting and reduce the minimum
MOSFET pulse width. As IBIAS is increased, however, the
current-limit trip voltage also increases. Figure 7 shows how
the trip voltage is established and how it varies with IBIAS. The
current sense resistor and IBIAS determine the peak value of
switch current. Since this current limiting is very fast, the trip
level of current is usually set to be well above the maximum
normal operating current (by a factor of 1.5 to 2). This
prevents false trips but still protects the MOSFET switch from
exceeding its pulse current ratings.
The driver circuit is a CMOS inverter whose typical
characteristics are shown in Figure 8. The n-channel (turn-off)
peak drive current is about 20% higher than that of the
p-channel (turn-on) device. Although the on-resistance
(rDS(on)) of the output drive is specified, usually the saturation
current (where ID/VDS is very small) determines the
switching speed. This is due to the vertical load line of
capacitive loads. In other words, the MOSFET gate
capacitance appears as a short circuit across the driver’s
The CMOS driver is fast enough to effectively eliminate cross-
conduction current during switching transitions, at least when
VCC 10 V. Above this level, a small amount of cross
conduction occurs. Therefore, the greatest gate drive
efficiency (approaching 100%) is achieved by keeping VCC
10 V, and the gate drive power is given by
Pgate = Qg x fs x VCC
Qg = MOSFET gate charge
fs = switching frequency
VCC = supply voltage
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