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SST39VF3201. 39VF3201 Datasheet

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SST39VF3201. 39VF3201 Datasheet






39VF3201 SST39VF3201. Datasheet pdf. Equivalent




39VF3201 SST39VF3201. Datasheet pdf. Equivalent





Part

39VF3201

Description

SST39VF3201



Feature


16 Mbit / 32 Mbit / 64 Mbit (x16) Multi- Purpose Flash Plus SST39VF1601 / SST39V F3201 / SST39VF6401 SST39VF1602 / SST39 VF3202 / SST39VF6402 SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MP F+ memories www.DataSheet4U.com Prelim inary Specifications FEATURES: • Org anized as 1M x16: SST39VF1601/1602 2M x 16: SST39VF3201/3202 4M x16: SST39VF640 1/6402 • Single Volt.
Manufacture

Silicon Storage Technology

Datasheet
Download 39VF3201 Datasheet


Silicon Storage Technology 39VF3201

39VF3201; age Read and Write Operations – 2.7-3. 6V • Superior Reliability – Enduran ce: 100,000 Cycles (Typical) – Greate r than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 9 mA (typical ) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical ) • Hardware Block-Protection/WP# Inp ut Pin – Top Block-Protection (top 32 .


Silicon Storage Technology 39VF3201

KWord) for SST39VF1602/3202/6402 – Bot tom Block-Protection (bottom 32 KWord) for SST39VF1601/3201/6401 • Sector-Er ase Capability – Uniform 2 KWord sect ors • Block-Erase Capability – Unif orm 32 KWord blocks • Chip-Erase Capa bility • Erase-Suspend/Erase-Resume C apabilities • Hardware Reset Pin (RST #) • Security-ID Feature – SST: 128 bits; User: 128 bits • Fast Read Acce.


Silicon Storage Technology 39VF3201

ss Time: – 70 ns – 90 ns • Latched Address and Data • Fast Erase and Wo rd-Program: – Sector-Erase Time: 18 m s (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms ( typical) – Word-Program Time: 7 µs ( typical) • Automatic Write Timing – Internal VPP Generation • End-of-Wri te Detection – Toggle Bits – Data# Polling • CMOS I/O Compatibility • JEDEC Stan.

Part

39VF3201

Description

SST39VF3201



Feature


16 Mbit / 32 Mbit / 64 Mbit (x16) Multi- Purpose Flash Plus SST39VF1601 / SST39V F3201 / SST39VF6401 SST39VF1602 / SST39 VF3202 / SST39VF6402 SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MP F+ memories www.DataSheet4U.com Prelim inary Specifications FEATURES: • Org anized as 1M x16: SST39VF1601/1602 2M x 16: SST39VF3201/3202 4M x16: SST39VF640 1/6402 • Single Volt.
Manufacture

Silicon Storage Technology

Datasheet
Download 39VF3201 Datasheet




 39VF3201
16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.coSSmT39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories
FEATURES:
Preliminary Specifications
• Organized as 1M x16: SST39VF1601/1602
2M x16: SST39VF3201/3202
4M x16: SST39VF6401/6402
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39VF1602/3202/6402
– Bottom Block-Protection (bottom 32 KWord)
for SST39VF1601/3201/6401
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Time:
– 70 ns
– 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm) for 16M and 32M
– 48-ball TFBGA (8mm x 10mm) for 64M
PRODUCT DESCRIPTION
The SST39VF160x/320x/640x devices are 1M x16, 2M
x16, and 4M x16 respectively, CMOS Multi-Purpose
Flash Plus (MPF+) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared
with alternate approaches. The SST39VF160x/320x/640x
write (Program or Erase) with a 2.7-3.6V power supply.
These devices conform to JEDEC standard pinouts for
x16 memories.
Featuring high performance Word-Program, the
SST39VF160x/320x/640x devices provide a typical Word-
Program time of 7 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program opera-
tion. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
typical endurance of 100,000 cycles. Data retention is rated
at greater than 100 years.
©2003 Silicon Storage Technology, Inc.
S71223-03-000
11/03
1
The SST39VF160x/320x/640x devices are suited for appli-
cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.




 39VF3201
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Pwrwewlim.DaintaaSrhyeSetp4Ue.cciofimcations
To meet high density, surface mount requirements, the
SST39VF160x/320x/640x are offered in 48-lead TSOP
and 48-ball TFBGA packages. See Figures 1 and 2 for
pin assignments.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39VF160x/320x/640x also have the Auto Low
Power mode which puts the device in a near standby
mode after data has been accessed with a valid Read
operation. This reduces the IDD active read current from
typically 9 mA to typically 3 µA. The Auto Low Power mode
reduces the typical IDD active read current to the range of 2
mA/MHz of Read cycle time. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no
access time penalty. Note that the device does not enter
Auto-Low Power mode after power-up with CE# held
steadily low, until the first address transition or CE# is
driven high.
Read
The Read operation of the SST39VF160x/320x/640x is
controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 3).
Word-Program Operation
The SST39VF160x/320x/640x are programmed on a
word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program
operation is accomplished in three steps. The first step is
the three-byte load sequence for Software Data Protection.
The second step is to load word address and word data.
During the Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is
the internal Program operation which is initiated after the
rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted within 10 µs. See Figures 4 and 5 for WE# and CE#
controlled Program operation timing diagrams and Figure
19 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform addi-
tional tasks. Any commands issued during the internal Pro-
gram operation are ignored. During the command
sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF160x/320x/640x offer both Sec-
tor-Erase and Block-Erase mode. The sector architecture
is based on uniform sector size of 2 KWord. The Block-
Erase mode is based on uniform block size of 32 KWord.
The Sector-Erase operation is initiated by executing a six-
byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte
command sequence with Block-Erase command (50H)
and block address (BA) in the last bus cycle. The sector or
block address is latched on the falling edge of the sixth
WE# pulse, while the command (30H or 50H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms and Figure 23 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
©2003 Silicon Storage Technology, Inc.
2
S71223-03-000
11/03




 39VF3201
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF160x/320x/640x provide a Chip-Erase oper-
ation, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
Preliminary Specifications
ing the completion of an internal Write operation, the
remaining data outputs may still be invalid: valid data on the
entire data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 20 for a flowchart.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 23 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF160x/320x/640x provide two software
means to detect the completion of a Write (Program or
Erase) cycle, in order to optimize the system write cycle
time. The software detection includes two status bits: Data#
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39VF160x/320x/640x are in the internal
Program operation, any attempt to read DQ7 will produce
the complement of the true data. Once the Program oper-
ation is completed, DQ7 will produce true data. Note that
even though DQ7 may have valid data immediately follow-
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 7 for Toggle Bit timing
diagram and Figure 20 for a flowchart.
TABLE 1: WRITE OPERATION STATUS
Status
DQ7 DQ6
DQ2
Normal Standard
Operation Program
DQ7# Toggle No Toggle
Standard
Erase
0 Toggle Toggle
Erase- Read from
Suspend Erase-Suspended
Mode
Sector/Block
1 1 Toggle
Read from
Data
Non- Erase-Suspended
Sector/Block
Data
Data
Program
DQ7# Toggle
N/A
T1.0 1223
Note: DQ7 and DQ2 require a valid address when reading
status information.
©2003 Silicon Storage Technology, Inc.
3
S71223-03-000
11/03



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