Reach Equalizer. DS22EV5110 Datasheet

DS22EV5110 Equalizer. Datasheet pdf. Equivalent

Part DS22EV5110
Description HDMI Extended Reach Equalizer
Feature DS22EV5110 DVI, HDMI Extended Reach Equalizer with Retimer and Output De-Emphasis www.DataSheet4U.c.
Manufacture National Semiconductor Corporation
Datasheet
Download DS22EV5110 Datasheet



DS22EV5110
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DS22EV5110
PRELIMINARY
May 11, 2009
DVI, HDMI Extended Reach Equalizer with Retimer and
Output De-Emphasis
General Description
The DS22EV5110 is a 6.75 Gbps (3 x 2.25 Gbps) extended
reach equalizer optimized for DVI™and HDMI™ cable exten-
sion applications with a high performance re-clocking feature.
It supports 3 Transition Minimized Differential Signaling
(TMDS®) data channels and a single clock channel over
DVI™ v1.0, and HDMI™ v1.3a data rates up to 2.25 Gbps for
each data channel. The device incorporates a configurable
receive equalizer, a clock and data recovery (CDR) circuit and
a de-emphasis driver on each data channel over DVI v1.0,
and HDMI v1.3a data rates up to 2.25 Gbps for each data
channel. The device incorporates a configurable receive
equalizer with a clock and data recovery (CDR) circuit on each
data channel. The clock channel feeds a high-perfromance
phase locked loop (PLL) that regenerates a low jitter output
clock for data recovery, enabling the extended reach of driv-
ing capability feature for repeater application.
The DS22EV5110 equalizes greater than 25 meters 28 AWG
of HDMI cable, enabling 1080p resolution with 12 bit deep
color depth (2.25 Gbps), to a low jitter version of the clock and
data signal outputs, reducing both deterministic and random
jitter. Obtaining total jitter is 0.09 UI or less over the supported
data rates. This extremely low level of output jitter provides
system designers with extra margin and flexibility when work-
ing with stringent timing budgets. It is ideal for the DVI and
HDMI source and repeater applications.
The transmitter supports configurable transmit de-emphasis
so the output can be optimized for driving additional lengths
of cables or FR4 traces.
Features
Optimized for HDMI/DVI source and repeater applications
TMDS compatible inputs with configurable receive
equalization supporting data rates up to 2.25 Gbps
TMDS compatible outputs with configurable transmit de-
emphasis
Dedicated CDR on each data channel reduces jitter
transfer
Resistor adjustable differential output voltage for AC
coupled Cat5e and Cat6 extension applications
2 equalizer settings for a wide range of cable reaches up
to 2.25 Gbps
Total Output Jitter of 0.09 UI at 2.25 Gbps
DVI 1.0 and HDMI v1.3a compatible TMDS source and
sink interface
7 mm x 7 mm 48 pin LLP package
>8 kV HBM ESD protection
0 °C to +70 °C operating temperature
Applications
Repeater Applications
HDMI / DVI Extender
Source Applications
Video Cards
Blu-ray DVD Players
Game Consoles
Sink Applications
High Definition Displays
Projectors
Application Diagram
© 2009 National Semiconductor Corporation 300949
30094953
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DS22EV5110
www.DataShPeeitn4U.Dcomescriptions
Pin Name Pin Number I/O, Type
Description
High Speed Differential I/O
C_IN−
C_IN+
D_IN0−
D_IN0+
D_IN1−
D_IN1+
D_IN2−
D_IN2+
C_OUT-
C_OUT+
1 I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50 terminating
2 resistor connects C_IN+ to VDD and C_IN- to VDD.
4 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 terminating
5 resistor connects D_IN0+ to VDD and D_IN0- to VDD.
8 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 terminating
9 resistor connects D_IN1+ to VDD and D_IN1- to VDD.
11 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 terminating
12 resistor connects D_IN2+ to VDD and D_IN2- to VDD.
36 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
35
D_OUT0− 33 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT0+
32
D_OUT1– 29 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT1+
28
D_OUT2− 26 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT2+
25
Equalization Control
EQ2
EQ1
EQ0
37 I, LVCMOS EQ2, EQ1 and EQ0 select the equalizer boost level for EQ channels. Internally pulled LOW
38 as default. See Table 1.
39
De-Emphasis Control
DE1
DE0
42 I, DE1, DE0 select the DE-emphasis level for output drivers. Internally pulled low as default.
43 LVCMOS Refer to Table 2.
Device Control
BYPASS
47 I, Reclocker enable control. Internally pulled low as default.
LVCMOS H = Reclock and De-Emphasis function is bypassed.
L = Normal operation.
EN 44 I, LVCMOS Enable Output Drivers. Internally pulled HIGH as default.
H = normal operation (enabled).
L = standby mode.
SD 45 O, LVCMOS Signal Detect Output pin.
H = signal detected on all channels.
L = no signal detected on one or more channels.
LOCK
14 O, LVCMOS Lock Indicator Output pin.
H = PLL is locked.
L = PLL is not locked.
VOD_CRL
48
I,
Analog
VOD control pin. Refer to Table 3. See Functional Description.
External resistance = 24 kto GND, Output DC Coupled Application.
External resistance = 12 kto GND, Output AC Coupled Application.
LFp 40 I, Loop filter capacitor pins.
LFn 41 Analog See Functional Description.
Power
VDD
3, 6, 7,
Power VDD = 3.3 V ±5%. VDD pins should be tied to the VDD plane through a low inductance path.
10, 13,
A 0.1 µF bypass capacitor should be connected between each VDD pin to the GND planes.
15, 46
See Power Supply Bypassing for additional details.
GND
22, 24,
27, 30,
31, 34
GND
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed
DAP
DAP
GND
Ground reference. The exposed pad at the center of the package must be connected to the
ground plane.
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