8-bit Microcontroller. AT83EC5135 Datasheet

AT83EC5135 Datasheet PDF, Equivalent


Part Number

AT83EC5135

Description

(AT83EC5134 - AT83EC5136) 8-bit Microcontroller

Manufacture

ATMEL Corporation

Total Page 30 Pages
PDF Download
Download AT83EC5135 Datasheet


AT83EC5135 Datasheet
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Features
80C52X2 Core (6 Clocks per Instruction)
– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode
– Dual Data Pointer
– Full-duplex Enhanced UART (EUART), TxD and Rxd are 5 Volt Tolerant
– Three 16-bit Timer/Counters: T0, T1 and T2
– 256 Bytes of Scratchpad RAM
8/16/32-Kbyte On-chip ROM
512 byte or 32-Kbyte EEPROM(1)
On-chip Expanded RAM (ERAM): 1024 Bytes
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
USB 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion (12Mbps)
– Endpoint 0 for Control Transfers: 32-byte FIFO
– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz DPLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to
6s at 4 MHz
Keyboard Interrupt Interface on Port P1 (8 Bits)
TWI (Two Wire Interface) 400Kbit/s
SPI Interface (Master/Slave Mode) MISO,MOSI,SCK and SS are 5 Volt Tolerant
34 I/O Pins
4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
4-level Priority Interrupt System (11 sources)
Idle and Power-down Modes
0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
Industrial Temperature Range
Low Voltage Range Supply: 2.7V to 3.6V
Packages: Die SO28, QFN32, MLF48, TQFP64
8-bit
Microcontroller
with Full Speed
USB Device
AT83C5134
AT83C5135
AT83C5136
Notes: 1. EEPROM only available on MLF48
Rev. 7683B–USB–03/07

AT83EC5135 Datasheet
www.DataSheet4U.com
Description
AT83C5134/35/36 are high performance ROM versions of the 80C51 single-chip 8-bit
microcontrollers with full speed USB functions.
AT83C5134/35 is pin compatible with AT89C5130A 16-Kbytes In-System Programma-
ble Flash microcontrollers. This allows to use AT89C5130A for development, pre-
production and flexibility, while using AT83C5134/35 for cost reduction in mass produc-
tion. Similarly AT83C5136 is pin compatible with AT89C5131A 32-Kbytes Flash
microcontroller.
AT83C5134/35/36 features a full-speed USB module compatible with the USB specifi-
cations Version 2.0. This module integrates the USB transceivers and the Serial
Interface Engine (SIE) with Digital Phase Locked Loop and 48 MHz clock recovery. USB
Event detection logic (Reset and Suspend/Resume) and FIFO buffers supporting the
mandatory control Endpoint (EP0) and 5 versatile Endpoints (EP1/EP2/EP3/EP4/EP5)
with minimum software overhead are also part of the USB module.
AT83C5134/35/36 retains the features of the Atmel 80C52 with extended ROM cpacity
(8/16/32 Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit
timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip
oscillator.
In addition, AT83C5134/35/36 has an on-chip expanded RAM of 1024 bytes (ERAM), a
dual- data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA),
up to 4 programmable LED current sources, a programmable hardware watchdog and a
power-on reset.
AT83C5134/35/36 has two software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers, the
serial ports and the interrupt system are still operating. In the power-down mode the
RAM is saved, the peripheral clock is frozen, but the device has full wake-up capability
through USB events or external interrupts.
2 AT83C5134/35/36
7683B–USB–03/07


Features Datasheet pdf www.DataSheet4U.com Features • 80C52X 2 Core (6 Clocks per Instruction) – M aximum Core Frequency 48 MHz in X1 Mode , 24 MHz in X2 Mode – Dual Data Point er – Full-duplex Enhanced UART (EUART ), TxD and Rxd are 5 Volt Tolerant – Three 16-bit Timer/Counters: T0, T1 and T2 – 256 Bytes of Scratchpad RAM 8/1 6/32-Kbyte On-chip ROM 512 byte or 32-K byte EEPROM(1) On-chip Expanded RAM (ER AM): 1024 Bytes Integrated Power Monito r (POR/PFD) to Supervise Internal Power Supply USB 2.0 Full Speed Compliant Mo dule with Interrupt on Transfer Complet ion (12Mbps) – Endpoint 0 for Control Transfers: 32-byte FIFO – 6 Programm able Endpoints with In or Out Direction s and with Bulk, Interrupt or Isochrono us Transfers • Endpoint 1, 2, 3: 32-b yte FIFO • Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode) – Suspend/Resume Interrupts – Power-on Reset and USB Bus Reset – 4 8 MHz DPLL for Full-speed Bus Operation – USB Bus Disconnection on Microcontroller Request 5 Channels Programmable Counter Array.
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