74AUP1T57 Datasheet (data sheet) PDF





74AUP1T57 Datasheet, Low-power Configurable Gate

74AUP1T57   74AUP1T57  

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www.DataSheet4U.com 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 01 — 3 January 2008 P roduct data sheet 1. General descripti on The 74AUP1T57 provides low-power, lo w-voltage configurable logic gate func tions. The output state is determined b y eight patterns of 3-bit input. The us er can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and

74AUP1T57 Datasheet, Low-power Configurable Gate

74AUP1T57   74AUP1T57  
buffer. All inputs can be connected to V CC or GND. This device ensures a very l ow static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T57 is designed fo r logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The w








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