NAND gate. 74HC03 Datasheet

74HC03 gate. Datasheet pdf. Equivalent

74HC03 Datasheet
Recommendation 74HC03 Datasheet
Part 74HC03
Description Quad 2-input NAND gate
Feature 74HC03; INTEGRATED CIRCUITS www.DataSheet4U.com DATA SHEET For a complete data sheet, please also download:.
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT03
Quad 2-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990



NXP Semiconductors 74HC03
Philips Semiconductors
www.DataSheet4U.com
Quad 2-input NAND gate
Product specification
74HC/HCT03
FEATURES
Level shift capability
Output capability: standard (open drain)
ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT03 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT03 provide the 2-input NAND function.
The 74HC/HCT03 have open-drain N-transistor outputs,
which are not clamped by a diode connected to VCC. In
the OFF-state, i.e. when one input is LOW, the output
may be pulled to any voltage between GND and VOmax.
This allows the device to be used as a LOW-to-HIGH or
HIGH-to-LOW level shifter. For digital operation and
OR-tied output applications, these devices must have a
pull-up resistor to establish a logic HIGH level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
tPZL/ tPLZ
CI
CPD
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per gate
CONDITIONS
TYPICAL
HC HCT
CL = 15 pF; RL = 1 k; VCC = 5 V 8
3.5
10
3.5
notes 1, 2 and 3
4.0 4.0
UNIT
ns
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2× fi + (CL × VCC2 × fo) + (VO2/RL) × duty factor LOW, where:
fi = input frequency in MHz
fo = output frequency in MHz
VO = output voltage in V
CL = output load capacitance in pF
VCC = supply voltage in V
RL = pull-up resistor in M
(CL × VCC2 × fo) = sum of outputs
(VO2/RL) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
3. The given value of CPD is obtained with:
CL = 0 pF and RL =
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2



NXP Semiconductors 74HC03
Philips Semiconductors
www.DataSheet4U.com
Quad 2-input NAND gate
PIN DESCRIPTION
PIN NO.
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
NAME AND FUNCTION
data inputs
data inputs
data outputs
ground (0 V)
positive supply voltage
Product specification
74HC/HCT03
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
OUTPUT
nA nB
LL
LH
HL
HH
nY
Z
Z
Z
L
Note
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
Fig.4 Functional diagram.
December 1990
Fig.5 Logic diagram (one gate).
3







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