GATE CMOS. TC58DVG02A1FT00 Datasheet
www.DataSheTetE4UN.cToAmTIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1-GBIT (128M u 8 BITS) CMOS NAND E2PROM
The TC58DVG02A1 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as 528 bytes u 32 pages u 8192 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes 512 bytes: 528 bytes
u 32 pages).
The TC58DVG02A1 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
Memory cell allay 528 u 256K u 8
528 u 8
(16K 512) bytes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read,
Multi Block Program, Multi Block Erase
x Mode control
x Power supply
VCC 2.7 V to 3.6 V
x Program/Erase Cycles 1E5 cycle (with ECC)
x Access time
Cell array to register 25 Ps max
Serial Read Cycle 50 ns min
x Operating current
Read (50 ns cycle) 10 mA typ.
10 mA typ.
10 mA typ.
50 PA max.
PIN ASSIGNMENT (TOP VIEW)
RY / BY
I/O1 to I/O8
Command latch enable
Address latch enable
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neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
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I/O Control circuit
Memory cell array
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage
Soldering Temperature (10s)
0.6 to 4.6
0.6 to 4.6
0.6 V to VCC 0.3 V (d 4.6 V)
55 to 150
0 to 70
CAPACITANCE *(Ta 25°C, f 1 MHz)
VIN 0 V
VOUT 0 V
* This parameter is periodically sampled and is not tested for every device.