A/D Converter. ADC16V130 Datasheet

ADC16V130 Converter. Datasheet pdf. Equivalent

Part ADC16V130
Description 130 MSPS A/D Converter
Feature ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs www.DataSheet4U.com April 8, 2009 ADC1.
Manufacture National Semiconductor
Datasheet
Download ADC16V130 Datasheet

ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs ADC16V130 Datasheet
ADC16V130 Datasheet
Recommendation Recommendation Datasheet ADC16V130 Datasheet





ADC16V130
www.DataSheet4U.com
ADC16V130
April 8, 2009
16-Bit, 130 MSPS A/D Converter with LVDS Outputs
General Description
The ADC16V130 is a monolithic high performance CMOS
analog-to-digital converter capable of converting analog input
signals into 16-bit digital words at rates up to 130 Mega Sam-
ples Per Second (MSPS). This converter uses a differential,
pipelined architecture with digital error correction and an on-
chip sample-and-hold circuit to minimize power consumption
and external component count while providing excellent dy-
namic performance. Automatic power-up calibration enables
excellent dynamic performance and reduces part-to-part vari-
ation, and the ADC16V130 could be re-calibrated at any time
by asserting and then de-asserting power-down. An integrat-
ed low noise and stable voltage reference and differential
reference buffer amplifier easies board level design. On-chip
duty cycle stabilizer with low additive jitter allows wide duty
cycle range of input clock without compromising its dynamic
performance. A unique sample-and-hold stage yields a full-
power bandwidth of 1.4 GHz. The digital data is provided via
full data rate LVDS outputs – making possible the 64-pin,
9mm x 9mm LLP package. The ADC16V130 operates on dual
power supplies +1.8V and +3.0V with a power-down feature
to reduce the power consumption to very low levels while al-
lowing fast recovery to full operation.
Features
Dual Supplies: 1.8V and 3.0V operation
On chip automatic calibration during power-up
Low power consumption
Multi-level multi-function pins for CLK/DF and PD
Power-down and sleep modes
On chip precision reference and sample-and-hold circuit
On chip low jitter duty-cycle stabilizer
Offset binary or 2's complement data format
Full data rate LVDS output port
64-pin LLP package (9x9x0.8, 0.5mm pin-pitch)
Key Specifications
Resolution
Conversion Rate
SNR
(fIN = 10MHz)
(fIN = 70MHz)
(fIN = 160MHz)
SFDR
(fIN = 10 MHz)
(fIN = 70MHz)
(fIN = 160MHz)
Full Power Bandwidth
Power Consumption
Core
LVDS Driver
Total
Operating Temperature Range
16 Bits
130 MSPS
  
78.5 dBFS (typ)
77.8 dBFS (typ)
76.7 dBFS (typ)
  
95.5 dBFS (typ)
92.0 dBFS (typ)
90.6 dBFS (typ)
1.4 GHz (typ)
  
650 mW (typ)
105 mW (typ)
755 mW (typ)
-40°C ~ 85°C
Applications
High IF Sampling Receivers
Multi-carrier Base Station Receivers
GSM/EDGE, CDMA2000, UMTS, LTE and WiMax
Test and Measurement Equipment
Communications Instrumentation
Data Acquisition
Portable Instrumentation
Block Diagram
© 2009 National Semiconductor Corporation 300626
30062602
www.national.com



ADC16V130
www.DataShCeeot4Un.cnomection Diagram
Ordering Information
Industrial (−40°C TA +85°C)
ADC16V130CISQ
ADC16V130EB
30062601
Package
64 Pin LLP
Evaluation Board
www.national.com
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