LVDS Buffer. DS25BR100 Datasheet

DS25BR100 Buffer. Datasheet pdf. Equivalent

Part DS25BR100
Description (DS25BR100 / DS25BR101) 3.125 Gbps LVDS Buffer
Feature DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization ww.
Manufacture National Semiconductor
Datasheet
Download DS25BR100 Datasheet

DS25BR100 3.125 Gbps LVDS Buffer with PE and EQ April 2007 DS25BR100 Datasheet
DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit P DS25BR100 Datasheet
DS25BR100 Datasheet
Recommendation Recommendation Datasheet DS25BR100 Datasheet





DS25BR100
www.DataSheet4U.com
DS25BR100 / DS25BR101
August 11, 2009
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and
Receive Equalization
General Description
The DS25BR100 and DS25BR101 are single channel 3.125
Gbps LVDS buffers optimized for high-speed signal trans-
mission over lossy FR-4 printed circuit board backplanes and
balanced metallic cables. Fully differential signal paths en-
sure exceptional signal integrity and noise immunity.
The DS25BR100 and DS25BR101 feature transmit pre-em-
phasis (PE) and receive equalization (EQ), making them ideal
for use as a repeater device. Other LVDS devices with similar
IO characteristics include the following products. The
DS25BR120 features four levels of pre-emphasis for use as
an optimized driver device, while the DS25BR110 features
four levels of equalization for use as an optimized receiver
device. The DS25BR150 is a buffer/repeater with the lowest
power consumption and does not feature transmit pre-em-
phasis nor receive equalization.
Wide input common mode range allows the receiver to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires minimal
space on the board while the flow-through pinout allows easy
board layout. On the DS25BR100 the differential input and
output is internally terminated with a 100resistor to lower
return losses, reduce component count and further minimize
board space. For added design flexibility the 100input ter-
minations on the DS25BR101 have been eliminated. This
enables a designer to adjust the termination for custom inter-
connect topologies and layout.
Features
DC - 3.125 Gbps low jitter, high noise immunity, low power
operation
Receive equalization reduces ISI jitter due to media loss
Transmit pre-emphasis drives lossy backplanes and
cables
On-chip 100input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space. The DS25BR101 eliminates the
on-chip input termination for added design flexibility.
7 kV ESD on LVDS I/O pins protects adjoining
components
Small 3 mm x 3 mm LLP-8 space saving package
Applications
Clock and data buffering
Metallic cable driving and equalization
FR-4 equalization
Typical Application
© 2009 National Semiconductor Corporation 201791
20179110
www.national.com



DS25BR100
www.DataShDeeet4vU.iccome Information
Device
Function
DS25BR100
DS25BR101
DS25BR110
DS25BR120
DS25BR150
Buffer / Repeater
Buffer / Repeater
Receiver
Driver
Buffer / Repeater
Ordering Information
NSID
DS25BR100TSD
DS25BR100TSDX
DS25BR101TSD
DS25BR101TSDX
Package
8 Lead LLP Package
8 Lead LLP Package
8 Lead LLP Package
8 Lead LLP Package
Block Diagram
Termination Option
Internal 100for LVDS inputs
External termination required
Internal 100for LVDS inputs
Internal 100for LVDS inputs
Internal 100for LVDS inputs
Available Signal
Conditioning
2 Levels: PE and EQ
2 Levels: PE and EQ
4 Levels: EQ
4 Levels: PE
None
Tape & Reel QTY
1000
4500
1000
4500
Package Number
SDA08A
SDA08A
SDA08A
SDA08A
Note: DS25BR101 eliminates 100input termination.
Pin Diagram
20179101
20179104
www.national.com
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