A/D Converter. ADC12V170 Datasheet

ADC12V170 Converter. Datasheet pdf. Equivalent

Part ADC12V170
Description 1.1 GHz Bandwidth A/D Converter
Feature ADC12V170 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs www.DataSheet4U.com .
Manufacture National Semiconductor
Datasheet
Download ADC12V170 Datasheet

ADC12V170 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter ADC12V170 Datasheet
ADC12V170 Datasheet
Recommendation Recommendation Datasheet ADC12V170 Datasheet





ADC12V170
www.DataSheet4U.com
ADC12V170
April 27, 2009
12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with
LVDS Outputs
General Description
The ADC12V170 is a high-performance CMOS analog-to-
digital converter with LVDS outputs. It is capable of converting
analog input signals into 12-Bit digital words at rates up to 170
Mega Samples Per Second (MSPS). Data leaves the chip in
a DDR (Dual Data Rate) format; this allows both edges of the
output clock to be utilized while achieving a smaller package
size. This converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize power consumption and the external com-
ponent count, while providing excellent dynamic perfor-
mance. A unique sample-and-hold stage yields a full-power
bandwidth of 1.1 GHz. The ADC12V170 operates from dual
+3.3V and +1.8V power supplies and consumes 781 mW of
power at 170 MSPS.
The separate +1.8V supply for the digital output interface al-
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 15 mW while
still allowing fast wake-up time to full operation. In addition
there is a sleep feature which consumes 50 mW of power and
has a faster wake-up time.
The differential inputs provide a full scale differential input
swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC12V170 can
be operated with an external reference.
Clock mode (differential versus single-ended) and output data
format (offset binary versus 2's complement) are pin-se-
lectable. A duty cycle stabilizer maintains performance over
a wide range of input clock duty cycles.
The ADC12V170 is pin-compatible with the ADC14V155. It is
available in a 48-lead LLP package and operates over the
industrial temperature range of −40°C to +85°C.
Features
1.1 GHz Full Power Bandwidth
Internal sample-and-hold circuit
Internal precision 1.0V reference
Single-ended or Differential clock modes
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V supply operation
Power-down and Sleep modes
Offset binary or 2's complement output data format
LVDS outputs
Pin-compatible: ADC14V155
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)
Key Specifications
Resolution
Conversion Rate
SNR (fIN = 70 MHz)
SFDR (fIN = 70 MHz)
ENOB (fIN = 70 MHz)
Full Power Bandwidth
Power Consumption
12 Bits
170 MSPS
67.2 dBFS (typ)
85.8 dBFS (typ)
10.9 bits (typ)
1.1 GHz (typ)
781 mW (typ)
Applications
High IF Sampling Receivers
Wireless Base Station Receivers
Power Amplifier Linearization
Multi-carrier, Multi-mode Receivers
Test and Measurement Equipment
Communications Instrumentation
Radar Systems
Block Diagram
© 2009 National Semiconductor Corporation 300168
30016802
www.national.com



ADC12V170
www.DataShCeeot4Un.cnomection Diagram
Ordering Information
Industrial (−40°C TA +85°C)
ADC12V170CISQ
ADC12V170LFEB
ADC12V170HFEB
30016801
Package
48 Pin LLP
Evaluation Board (fIN<150 MHz)
Evaluation Board (fIN>150 MHz)
www.national.com
2





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)