Microcircuit. AS4DDR16M72PBG Datasheet

AS4DDR16M72PBG Datasheet PDF


Part

AS4DDR16M72PBG

Description

16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

Manufacture

Austin Semiconductor

Page 19 Pages
Datasheet
Download AS4DDR16M72PBG Datasheet


AS4DDR16M72PBG Datasheet
iPEM
1.2 Gb SDRAM-DDR
Austin Semiconductor, Inc. AS4DDR16M72PBG
16Mx72 DDR SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
„ DDR SDRAM Data Rate = 200, 250, 266, 333Mbps
„ Package:
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
„ 2.5V ±0.2V core power supply
„ 2.5V I/O (SSTL_2 compatible)
„ Differential clock inputs (CLK and CLK#)
„ Commands entered on each positive CLK edge
„ Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
„ Programmable Burst length: 2,4 or 8
„ Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
„ DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
„ DLL to align DQ and DQS transitions with CLK
„ Four internal banks for concurrent operation
„ Two data mask (DM) pins for masking write data
„ Programmable IOL/IOH option
„ Auto precharge option
„ Auto Refresh and Self Refresh Modes
„ Industrial, Enhanced and Military Temperature
Ranges
„ Organized as 16M x 72/80
„ Weight: AS4DDR16M72PBG = 3.50 grams typical
* This product and or it’s specifications is subject to change without notice..
BENEFITS
„ 40% SPACE SAVINGS
„ Reduced part count
„ Reduced I/O count
34% I/O Reduction
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Laminate interposer for optimum TCE match
„ Upgradeable to 32M x 72 density
(AS4DDR32M72PBG)
„ Meets or exceeds published specifications of
White’s W3E16M72S-XBX
www.DataSheet4U.com
Monolithic Solution
Integrated MCP Solution
O 11.9 11.9 11.9 11.9 11.9
P
T
I
22.3
O
N
S
Area
I/O
Count
5 x 265mm2 = 1328mm2 Plus
5 x 66 pins = 320 pins
32
800mm2
219 Balls
S
A
V
25 I
N
G
S
40+%
34 %
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

AS4DDR16M72PBG Datasheet
iPEM
1.2 Gb SDRAM-DDR
Austin Semiconductor, Inc. AS4DDR16M72PBG
SDRAM-DDR PINOUT TOP VIEW
DQ0 DQ14 DQ15 VSS VSS A9 A10 A11 A8 VCCQ VCCQ DQ16 DQ17 DQ31 VSS
DQ1 DQ2 DQ12 DQ13 VSS VSS A0 A7 A6 A1 VCC VCC DQ18 DQ19 DQ29 DQ30
DQ3 DQ4 DQ10 DQ11 VCC VCC A2 A5 A4 A3 VSS VSS DQ20 DQ21 DQ27 DQ28
DQ6 DQ5 DQ8 DQ9 VCCQ VSSQ A12 DNU DNU DNU VSS VSS DQ22 DQ23 DQ26 DQ25
DQ7 DQML0 VCC DQMH0 DQSH3 DQSL0 DQSH0 BA0 BA1 DQSL1 DQSH1 VREF DQML1 VSS NC DQ24
CA S0\ WE0\ VCC CLK0 DQSL3
RAS1\ WE1\ VSS DQMH1 CLK1
CS0\ RAS0\ VCC CKE0 CLKO\
CAS\ CS1\ VSS CLK1\ CKE1
VSS VSS VCC VCCQ VSS
VCC VSS VSS VCCQ VCC
VSS VSS VCC VCCQ VSS
VCC VSS VSS VCCQ VCC
CLK3\ CKE3 VCC CS3\ DQSL4
CLK2\ CKE2 VSS RAS2\ CS2\
NC CLK3 VCC CAS3\ RAS3\
DQSL2 CLK2 VSS WE2\ CAS2\
DQ56 DQMH3 VCC WE3\ DQML3 CKE4 DQMH4 CLK4 CAS4\ WE4\ RAS4\ CS4\ DQMH2 VSS DQML2 DQ39
DQ57 DQ58 DQ55 DQ54 DQSH4 CLK4\ DQ73 DQ72 DQ71 DQ70 DQML4 DQSH2\ DQ41 DQ40 DQ37 DQ38
www.DataSDhQe6e0t4U.DcoQm59 DQ53 DQ52 VSS VSS DQ75 DQ74 DQ69 DQ68 VCC VCC DQ43 DQ42 DQ36 DQ35
DQ62 DQ61 DQ51 DQ50 VCC VCC DQ77 DQ76 DQ67 DQ66 VSS VSS DQ45 DQ44 DQ34 DQ33
VSS DQ63 DQ49 DQ48 VCCQ VCCQ DQ79 DQ78 DQ65 DQ64 VSS VSS DQ47 DQ46 DQ32 VCC
Ground
Array Power
CNTRL
D/Q Power
Address
Data IO
Address/DNU
UNPOPULATED
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2


Features Datasheet pdf i PEM 1.2 G b SDRAM-DDR Gb Austin Semico nductor, Inc. AS4DDR16M72PBG 16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ DDR SDRAM Data Rate = 200, 250, 266, 333Mbps „ Packa ge: BENEFITS „ 40% SPACE SAVINGS „ R educed part count „ Reduced I/O count • „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ 219 Plastic Ball Gri d Array (PBGA), 32 x 25mm 2.5V ±0.2V c ore power supply 2.5V I/O (SSTL_2 compa tible) Differential clock inputs (CLK a nd CLK#) Commands entered on each posit ive CLK edge Internal pipelined double- data-rate (DDR) architecture; two data accesses per clock cycle Programmable B urst length: 2,4 or 8 Bidirectional dat a strobe (DQS) transmitted/received wit h data, i.e., source-synchronous data c apture (one per byte) DQS edge-aligned with data for READs; center-aligned wit h data for WRITEs DLL to align DQ and D QS transitions with CLK Four internal b anks for concurrent operation Two data mask (DM) pins for masking write data Programmable IOL/IOH option Auto precharge option .
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