Microcircuit. AS4DDR232M64PBG Datasheet

AS4DDR232M64PBG Datasheet PDF


Part

AS4DDR232M64PBG

Description

32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

Manufacture

Austin Semiconductor

Page 28 Pages
Datasheet
Download AS4DDR232M64PBG Datasheet


AS4DDR232M64PBG Datasheet
iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc. AS4DDR232M64PBG
32Mx64 DDR2 SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
„ DDR2 Data rate = 667, 533, 400
„ Available in Industrial, Enhanced and Military Temp
„ Package:
255 Plastic Ball Grid Array (PBGA), 25 x 32mm
1.27mm pitch
„ Differential data strobe (DQS, DQS#) per byte
„ Internal, pipelined, double data rate architecture
„ 4-bit prefetch architecture
„ DLL for alignment of DQ and DQS transitions with
clock signal
„ Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
„ Programmable Burst lengths: 4 or 8
„ Auto Refresh and Self Refresh Modes
„ On Die Termination (ODT)
„ Adjustable data – output drive strength
„ 1.8V ±0.1V power supply and I/O (VCC/VCCQ)
„ Programmable CAS latency: 3, 4, 5, or 6
„ Posted CAS additive latency: 0, 1, 2, 3 or 4
„ Write latency = Read latency - 1* tCK
„ Organized as 32M x 64
„ Weight: AS4DDR232M64PBG ~ 3.5 grams typical
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
BENEFITS
„ SPACE conscious PBGA defined for easy
SMT manufacturability (50 mil ball pitch)
„ Reduced part count
„ 47% I/O reduction vs Individual CSP approach
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Upgradable to 64M x 64 density
(consult factory for info on
AS4DDR264M64PBG)
ConfigurationAddressing
Parameter
Configuration
RefreshCount
RowAddress
BankAddress
ColumnAddress
32Megx72
8Megx16x4Banks
8K
8K(A0ͲA12)
4(BA0ͲBA1)
1K(A0ͲA9)
www.DaFtaUSNheCet4TUI.OcoNm AL BLOCK DIAGRAM
Ax, BA0-2
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VCCL
VSSDL
CS0\
CS1\
CS2\
CS3\
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
RASx\,CASx\,WEx\
CKx,CKx\,CKEx
A
2
2
2
3
3
VCCL
VSSDL
A2
2
2
3
3
DQ0-15 B
VCCL
VSSDL
B2
2
2
3
3
DQ16-31 C
VCCL
VSSDL
C2
2
2
3
3
DQ32-47 D
D
DQ48-63
AS4DDR232M64PBG
Rev. 1.3 6/09
Austin Semiconductor, Inc. Austin, Texas 512.339.1188 www.austinsemiconductor.com
1

AS4DDR232M64PBG Datasheet
iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc. AS4DDR232M64PBG
SDRAM-DDRII PINOUT TOP VIEW
,
123456
A DQ0 DQ14 DQ15 VSS VSS
7
A9
89
A10 A11
10 11 12 13 14 15 16
A8 VCCQ VCCQ DQ16 DQ17 DQ31 VSS A
B DQ1 DQ2 DQ12 DQ13 VSS VSS
A0
A7
A6
A1 VCC VCC DQ18 DQ19 DQ29 DQ30 B
C DQ3 DQ4 DQ10 DQ11 VCC VCC
A2
A5
A4
A3 VSS VSS DQ20 DQ21 DQ27 DQ28 C
D DQ6 DQ5 DQ8 DQ9 VCCQ VCCQ A12/NC DNU DNU DNU VSS VSS DQ22 DQ23 DQ26 DQ25 D
E DQ7 LDM0 VCC UDM0 UDQS3 LDQS0 UDQS0 BA0
BA1 LDQS1 UDQS1 VREF LDM1 VSS
NC DQ24 E
F CAS0\ WE0\ VCC CLK0 LDQS3 UDQS3\ LDQS0\ UDQS0\ NC UDQS1\ LDQS1\ RAS1\ WE1\ VSS UDM1 CLK1 F
G CS0\ RAS0\ VCC CKE0 CLK0\ LDQS3\ VSSQ VSSQ VSSQ VSSQ NC CAS1\ CS1\ VSS CLK1\ CKE1 G
H VSS VSS VCC VCCQ VSS
NC VSSQ VSSQ VSSQ VSSQ NC
VCC VSS VSS VCCQ VCC H
J VSS VSS VCC VCCQ VSS
NC VSSQ VSSQ VSSQ VSSQ NC
VCC VSS VSS VCCQ VCC J
K CLK3\ CKE3 VCC CS3\ NC
NC VSSQ VSSQ VSSQ VSSQ NC CLK2\ CKE2 VSS RAS2\ CS2\ K
L NC CLK3 VCC CAS3\ RAS3\ ODT NC NC NC LDQS2\ UDQS2\ LDQS2 CLK2 VSS WE2\ CAS2\ L
M DQ56 UDM3 VCC WE3\ LDM3 NC NC NC NC NC NC NC UDM2 VSS LDM2 DQ39 M
N DQ57 DQ58 DQ55 DQ54 NC NC NC NC NC NC NC UDQS2 DQ41 DQ40 DQ37 DQ38 N
P DQ60 DQ59 DQ53 DQ52 VSS VSS NC NC NC NC VCC VCC DQ43 DQ42 DQ36 DQ35 P
R DQ62 DQ61 DQ51 DQ50 VCC VCC NC NC NC NC VSS VSS DQ45 DQ44 DQ34 DQ33 R
www.DataTSheVeSt4SU.coDmQ63 DQ49 DQ48 VCCQ VCCQ NC NC NC NC VSS VSS DQ47 DQ46 DQ32 VCC T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Ground
Level REF.
Array Power
CNTRL
D/Q Power
ADDRESS-DNU
Address
UNPOPULATED
Data IO
NC
Note 1: Ball location D9 is reserved for future use on 64M x 64 in which it will be BANKSELECT2 ‘BA2’. Ball D10 is reserved for future use
on 128M x 64 in which it will be A13.
Important Note: It is recommended that no bias be applied to either the DNU or NC pins. They are not connected to any die pad but DNU &
NC pins may be shorted together in package.
AS4DDR232M64PBG
Rev. 1.3 6/09
Austin Semiconductor, Inc. Austin, Texas 512.339.1188 www.austinsemiconductor.com
2


Features Datasheet pdf i PEM 2.1 G b SDRAM-DDR2 Gb Austin Semic onductor, Inc. AS4DDR232M64PBG 32Mx64 D DR2 SDRAM iNTEGRATED Plastic Encapsulat ed Microcircuit FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400 Availab le in Industrial, Enhanced and Military Temp Package: • 255 Plastic Ball Gri d Array (PBGA), 25 x 32mm • 1.27mm pi tch Differential data strobe (DQS, DQS# ) per byte Internal, pipelined, double data rate architecture 4-bit prefetch a rchitecture DLL for alignment of DQ and DQS transitions with clock signal Four internal banks for concurrent operatio n (Per DDR2 SDRAM Die) Programmable Bur st lengths: 4 or 8 Auto Refresh and Sel f Refresh Modes On Die Termination (ODT ) Adjustable data – output drive stre ngth 1.8V ±0.1V power supply and I/O ( VCC/VCCQ) Programmable CAS latency: 3, 4, 5, or 6 Posted CAS additive latency: 0, 1, 2, 3 or 4 Write latency = Read l atency - 1* tCK Organized as 32M x 64 W eight: AS4DDR232M64PBG ~ 3.5 grams typical BENEFITS „ „ „ „ „ „ SPACE conscious PBGA de.
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