AT26DF081A. 26DF081A Datasheet
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
• 70 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
• Optimized Physical Sectoring for Code Shadowing and Code + Data Storage
– One 32-Kbyte Top Boot Sector
– Two 8-Kbyte Sectors
– One 16-Kbyte Sector
– Fifteen 64-Kbyte Sectors
• Individual Sector Protection for Program/Erase Protection
• Hardware Controlled Locking of Protected Sectors
• Flexible Programming Options
– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 11 µA Deep Power-down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 200-mil wide)
The AT26DF081A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT26DF081A, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF081A have been opti-
mized to meet the needs of today’s code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
The AT26DF081A also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments.
Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and
erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for
programming and erasing.
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
CS accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
SI including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
www.DataSheet4WUR.coITmE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
section “Protection Commands and Features” on page 14 for more details on protection features
and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold”
on page 26 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to VCC whenever
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
GROUND: The ground reference for the power supply. GND should be connected to the
2 AT26DF081A [Preliminary]