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Burst Architecture. CY7C1163V18 Datasheet

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Burst Architecture. CY7C1163V18 Datasheet






CY7C1163V18 Architecture. Datasheet pdf. Equivalent




CY7C1163V18 Architecture. Datasheet pdf. Equivalent





Part

CY7C1163V18

Description

(CY7C11xxV18) SRAM 4-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1163V18 Datasheet


Cypress Semiconductor CY7C1163V18

CY7C1163V18; CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C 1165V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Lat ency) Features ■ Functional Descript ion The CY7C1161V18, CY7C1176V18, CY7C1 163V18, and CY7C1165V18 are 1.8V Synchr onous Pipelined SRAMs equipped with QDR ™-II+ architecture. QDR-II+ architect ure consists of two separate ports to a ccess the memory array. .


Cypress Semiconductor CY7C1163V18

The read port has dedicated data outputs to support read operations and the wri te port has dedicated data inputs to su pport write operations. QDR-II+ archite cture has separate data inputs and data outputs to completely eliminate the ne ed to turn around the data bus that is required with common IO devices. Each p ort can be accessed through a common ad dress bus. Address.


Cypress Semiconductor CY7C1163V18

es for read and write addresses are latc hed onto alternate rising edges of the input (K) clock. Accesses to the QDR-II + read and write ports are completely i ndependent of one another. In order to maximize data throughput, both read and write ports are equipped with Double D ata Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1161V1.



Part

CY7C1163V18

Description

(CY7C11xxV18) SRAM 4-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1163V18 Datasheet




 CY7C1163V18
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
18-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
Separate independent read and write data ports
Supports concurrent transactions
300 MHz to 400 MHz clock for high bandwidth
4-word burst to reduce address bus frequency
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 800 MHz) at 400 MHz
Read latency of 2.5 clock cycles
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
Available in x8, x9, x18, and x36 configurations
Full data coherency providing most current data
Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
www.DJaTtaASGhe1e1t44U9..c1ocmompatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
With cycle read latency of 2.5 cycles:
CY7C1161V18 – 2M x 8
CY7C1176V18 – 2M x 9
CY7C1163V18 – 1M x 18
CY7C1165V18 – 512K x 36
Functional Description
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and
CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs
equipped with QDR™-II+ architecture. QDR-II+ architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to turn around the
data bus that is required with common IO devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched onto alternate rising edges
of the input (K) clock. Accesses to the QDR-II+ read and write
ports are completely independent of one another. In order to
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words
(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks K and K, memory bandwidth is maximized while simpli-
fying system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects for each port.
Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the or K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
400 MHz
400
1080
375 MHz
375
1020
333 MHz
333
920
300 MHz
300
850
Unit
MHz
mA
Note
1.
The QDR consortium
= 1.4V to VDD.
specification
for
VDDQ
is
1.5V
+
0.1V.
The
Cypress
QDR
devices
exceed
the
QDR
consortium
specification
and
are
capable
of
supporting
VDDQ
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06582 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 15, 2007
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 CY7C1163V18
Logic Block Diagram (CY7C1161V18)
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
D[7:0] 8
A(18:0) 19
K
K
DOFF
Address
Register
CLK
Gen.
VREF
WPS
NWS[1:0]
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19 A(18:0)
Read Data Reg.
32 16
16
Control
Logic
RPS
Reg.
Reg.
Reg.
8
8
CQ
CQ
Q[7:0]
QVLD
Logic Block Diagram (CY7C1176V18)
www.DataSheet4U.com D[8:0] 9
A(18:0) 19
K
K
DOFF
Address
Register
CLK
Gen.
VREF
WPS
BWS[0]
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19 A(18:0)
Read Data Reg.
36 18
18
Control
Logic
RPS
Reg.
Reg.
Reg.
9
9
CQ
CQ
Q[8:0]
QVLD
Document Number: 001-06582 Rev. *C
Page 2 of 29
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 CY7C1163V18
Logic Block Diagram (CY7C1163V18)
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
D[17:0] 18
A(17:0) 18
K
K
DOFF
Address
Register
CLK
Gen.
VREF
WPS
BWS[1:0]
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
18 A(17:0)
Read Data Reg.
72 36
36
Control
Logic
RPS
Reg.
Reg.
Reg.
18
18
CQ
CQ
Q[17:0]
QVLD
Logic Block Diagram (CY7C1165V18)
www.DataSheet4U.com D[35:0] 36
A(16:0) 17
K
K
DOFF
VREF
WPS
BWS[3:0]
Address
Register
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
17 A(16:0)
Read Data Reg.
144 72
72
Control
Logic
RPS
Reg.
Reg.
Reg.
36
36
CQ
CQ
Q[35:0]
QVLD
Document Number: 001-06582 Rev. *C
Page 3 of 29
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