Burst PSRAM. M36P0R9060N0 Datasheet

M36P0R9060N0 PSRAM. Datasheet pdf. Equivalent


Part M36P0R9060N0
Description 512 Mbit Flash memory 64 Mbit (Burst) PSRAM
Feature M36P0R9060N0 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.
Manufacture Numonyx
Datasheet
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M36P0R9060N0 512 Mbit (x16, Multiple Bank, Multi-Level, Burs M36P0R9060N0 Datasheet
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M36P0R9060N0
M36P0R9060N0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
64 Mbit (Burst) PSRAM, 1.8V supply, Mux I/O, Multi-Chip Package
Preliminary Data
Feature summary
Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
Bank, Multi-Level, Burst) Flash memory
– 1 die of 64 Mbit (4Mb x16) PSRAM
Supply voltage
– VDDF = VCCP = VDDQ = 1.7 to 1.95V
– VPPF = 9V for fast program
Electronic signature
– Manufacturer Code: 20h
– Device Code: 8833
ECOPACK® package
Flash memory
Multiplexed Address/Data
Synchronous / Asynchronous Read
– Synchronous Burst Read mode:
108MHz, 66MHz
– Asynchronous Page Read mode
– Random Access: 96ns
Programming time
– 4.2µs typical Word program time using
www.DataSheet4UB.cuomffer Enhanced Factory Program
command
Memory organization
– Multiple Bank Memory Array: 64 Mbit
Banks
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
FBGA
TFBGA107 (ZAN)
100,000 Program/erase cycles per block
Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
Common Flash Interface (CFI)
PSRAM
Multiplexed Address/Data bus
Asynchronous operating modes
– Random Read: 70ns access time
– Asynchronous Write
Synchronous modes
– Synchronous Read: Fixed length (4-, 8-,
16-, and 32-Word) or continuous burst
– Clock Frequency: 83MHz (max)
– Synchronous Write: continuous burst
Low-power features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) mode
– Automatic Temperature-compensated Self-
Refresh
November 2007
Rev 0.2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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www.numonyx.com
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M36P0R9060N0
Contents
M36P0R9060N0
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Address Inputs (ADQ0-ADQ15 and A16-A24) . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
www.DataSheet4U.com
2.18
2.19
2.20
2.21
2.22
Flash Chip Enable input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Output Enable inputs (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 11
Deep Power-Down input (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCCP Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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