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CY7C1371DV25

Cypress Semiconductor
Part Number CY7C1371DV25
Manufacturer Cypress Semiconductor
Description (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
Published Mar 12, 2010
Detailed Description CY7C1371DV25 com CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Fea...
Datasheet PDF File CY7C1371DV25 PDF File

CY7C1371DV25
CY7C1371DV25

Overview
CY7C1371DV25 com CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.
5V core power supply (VDD) • 2.
5V I/O power supply (VDDQ) • Fast clock-to-output times — 6.
5 ns (for 133-MHz device) • Clock Enable (CEN) pin to enable clock and susp...


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