Stack Memory. AT52BC3221A Datasheet

AT52BC3221A Datasheet PDF, Equivalent


Part Number

AT52BC3221A

Description

32-Mbit Flash 8-Mbit PSRAM Stack Memory

Manufacture

ATMEL Corporation

Total Page 30 Pages
PDF Download
Download AT52BC3221A Datasheet PDF


AT52BC3221A Datasheet
Features
32-Mbit Flash and 4-Mbit/8-Mbit PSRAM
Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
2.7V to 3.3V Operating Voltage
Flash
32-megabit (2M x 16)
2.7V to 3.3V Read/Write
Access Time – 70 ns
Sector Erase Architecture
– Sixty-three 32K Word Sectors with Individual Write Lockout
– Eight 4K Word Sectors with Individual Write Lockout
Fast Word Program Time – 15 µs
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 12 mA Active
– 13 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
PSRAM
8-megabit (512K x 16)
2.7V to 3.3V VCC
70 ns Access Time
Extended Temperature Range
ISB0 < 10 µA when Deep Power-Down
www.DataSheet4U.com
32-Mbit Flash +
8-Mbit PSRAM
Stack Memory
AT52BC3221A
AT52BC3221AT
Preliminary
Device Number
AT52BC3221A
AT52BC3221AT
Flash Boot
Location
Bottom
Top
Flash Plane
Configuration
32M (2M x 16)
32M (2M x 16)
PSRAM
Configuration
8M (512K x 16)
8M (512K x 16)
Rev. 3466A–STKD–11/04
1

AT52BC3221A Datasheet
Pin Configuration
CBGA (Top View)
Pin Name
A0 - A18, A19 - A20
CE
OE
WE
RESET
RDY/BUSY
VPP
VCC
GND
I/O0 - I/O15
NC
PLB
PUB
PVCC
PGND
PCS1
ZZ
PWE
POE
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Function
Common Address Input for 8M PSRAM/Flash, Flash Address Input
Flash Chip Enable
Flash Output Enable
Flash Write Enable
Flash Reset
Flash READY/BUSY Output
Flash Power Supply for Accelerated Program/Erase Operations
Flash Power
Flash Ground
Data Inputs/Outputs
No Connect
PSRAM Lower Byte
PSRAM Upper Byte
PSRAM Power
PSRAM Ground
PSRAM Chip Select 1
Low Power Modes
PSRAM Write Enable
PSRAM Output Enable
1 2 3 4 5 6 7 8 9 10 11 12
A
NC NC A20 A11 A15 A14 A13 A12 GND NC NC NC
B
A16 A8 A10 A9 I/O15 PWE I/O14 I/O7
C
WE RDY/BUSY
I/O13 I/O6 I/O4 I/O5
D
PGND RESET
I/O12 ZZ PVCC VCC
E
NC VPP A19 I/O11
I/O10 I/O2 I/O3
F
PLB PUB POE
I/O9 I/O8 I/O0 I/O1
G
A18 A17 A7 A6 A3 A2 A1 PCS1
H
NC NC NC A5 A4 A0 CE GND OE NC NC NC
2 AT52BC3221A(T)
3466A–STKD–11/04


Features Datasheet pdf Features • 32-Mbit Flash and 4-Mbit/8- Mbit PSRAM • Single 66-ball (8 mm x 1 0 mm x 1.2 mm) CBGA Package • 2.7V to 3.3V Operating Voltage www.DataSheet4 U.com Flash • • • • • • 32 -megabit (2M x 16) 2.7V to 3.3V Read/Wr ite Access Time – 70 ns Sector Erase Architecture – Sixty-three 32K Word S ectors with Individual Write Lockout Eight 4K Word Sectors with Individual Write Lockout Fast Word Program Time 15 µs Suspend/Resume Feature for Er ase and Program – Supports Reading an d Programming from Any Sector by Suspen ding Erase of a Different Sector – Su pports Reading Any Word by Suspending P rogramming of Any Other Word Low-power Operation – 12 mA Active – 13 µA S tandby Data Polling, Toggle Bit, Ready/ Busy for End of Program Detection VPP P in for Write Protection and Accelerated Program/Erase Operations RESET Input f or Device Initialization Sector Lockdow n Support Top or Bottom Boot Block Conf iguration Available 128-bit Protection Register Minimum 100,000 Erase Cycles 32-Mbit Flash + 8-Mbi.
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