Mode. IC41LV16257S Datasheet

IC41LV16257S Datasheet PDF


Part

IC41LV16257S

Description

256Kx16 bit Dynamic RAM with Fast Page Mode

Manufacture

Integrated Circuit Solution

Page 20 Pages
Datasheet
Download IC41LV16257S Datasheet


IC41LV16257S Datasheet
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
Document Title
256Kx16 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
0A
History
Initial Draft
www.DataSheet4U.com
Draft Date
Remark
August 11,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
1

IC41LV16257S Datasheet
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
www.DataSheet4U.com
256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
DESCRIPTION
• Fast access and cycle time
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode: RAS-Only, CAS-before-RAS
(CBR), Hidden
• Self Refresh Mode: 512 cycles/64 ms (S version
only)
• JEDEC standard pinout
• Single power supply:
The ICSI IC41C16257 and the IC41LV16257 are 262,144
x 16-bit high-performance CMOS Dynamic Random Access
Memory. Fast Page Mode allows 512 random accesses
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
byte, makes these devices ideal for use in 16-, 32-bit wide
data bus systems.
These features make the IC41C16257 and the IC41LV16257
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
— 5V ± 10% (IC41C16257)
— 3.3V ± 10% (IC41LV16257)
The IC41C16257 and the IC41LV16257 are packaged in a
40-pin, 400mil SOJ and TSOP-2.
• Byte Write and Byte Read operation via
two CAS
• Available in 40-pin SOJ and TSOP-2
PIN CONFIGURATIONS
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
-35 -50 -60 Unit
35 50 60 ns
10 14 15 ns
18 25 30 ns
12 20 25 ns
60 90 110 ns
40-Pin TSOP-2
40-Pin SOJ
PIN DESCRIPTIONS
A0-A8
Address Inputs
I/O0-I/O15
WE
OE
RAS
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
UCAS
LCAS
Upper Column Address
Strobe
Lower Column Address
Strobe
Vcc Power
GND
Ground
NC No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
DR021-0A 08/11/2001


Features Datasheet pdf IC41C16257/IC41C16257S IC41LV16257/IC41L V16257S www.DataSheet4U.com Document T itle 256Kx16 bit Dynamic RAM with Fast Page Mode Revision History Revision No 0A History Initial Draft Draft Date August 11,2001 Remark The attached da tasheets are provided by ICSI. Integrat ed Circuit Solution Inc reserve the rig ht to change the specifications and pro ducts. ICSI will answer to your questio ns about device. If you have any questi ons, please contact the ICSI offices. Integrated Circuit Solution Inc. DR021- 0A 08/11/2001 1 IC41C16257/IC41C16257 S IC41LV16257/IC41LV16257S www.DataShee t4U.com 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE FEATURES • • • • • • DESCRIPTION • The ICSI IC41C16257 and the IC41LV16 257 are 262,144 Fast access and cycle t ime x 16-bit high-performance CMOS Dyna mic Random Access TTL compatible inputs and outputs Memory. Fast Page Mode all ows 512 random accesses Refresh Interva l: 512 cycles/8 ms within a single row with access cycle time as short as 12 ns p.
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