DatasheetsPDF.com

SigmaQuad-II Burst. GS8342D09E-250 Datasheet

DatasheetsPDF.com

SigmaQuad-II Burst. GS8342D09E-250 Datasheet






GS8342D09E-250 Burst. Datasheet pdf. Equivalent




GS8342D09E-250 Burst. Datasheet pdf. Equivalent





Part

GS8342D09E-250

Description

36Mb SigmaQuad-II Burst



Feature


Preliminary GS8342D08/09/18/36E-333/300/ 250/200/167 www.DataSheet4U.com 165-Bum p BGA Commercial Temp Industrial Temp F eatures • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-stand ard pinout and package • Dual Double Data Rate interface • Byte Write cont rols sampled at data-in time • Burst of 4 Read and Write • 1.8 V +100/–1 00 mV core power supply • 1.5 V or.
Manufacture

GSI Technology

Datasheet
Download GS8342D09E-250 Datasheet


GSI Technology GS8342D09E-250

GS8342D09E-250; 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programm able output drive strength • IEEE 114 9.1 JTAG-compliant Boundary Scan • 16 5-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available • Pin-compatib le with present 9Mb and 18Mb and future 72Mb and 144Mb devices 36Mb Si.


GSI Technology GS8342D09E-250

gmaQuad-II Burst of 4 SRAM 167 MHz–33 3 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Bo ttom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array C cl ock inputs. C and C are also independen t single-ended clock inputs, not differ ential inputs. If the C clocks are tied high, the K clocks are routed internal ly to fire the output registers instead . Because Separate I.


GSI Technology GS8342D09E-250

/O SigmaQuad-II B4 RAMs always transfer data in four packets, A0 and A1 are int ernally set to 0 for the first read or write transfer, and automatically incre mented by 1 for the next transfers. Bec ause the LSBs are tied off internally, the address field of a SigmaQuad-II B4 RAM is always two address pins less tha n the advertised index depth (e.g., the 2M x 18 has a 512.

Part

GS8342D09E-250

Description

36Mb SigmaQuad-II Burst



Feature


Preliminary GS8342D08/09/18/36E-333/300/ 250/200/167 www.DataSheet4U.com 165-Bum p BGA Commercial Temp Industrial Temp F eatures • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-stand ard pinout and package • Dual Double Data Rate interface • Byte Write cont rols sampled at data-in time • Burst of 4 Read and Write • 1.8 V +100/–1 00 mV core power supply • 1.5 V or.
Manufacture

GSI Technology

Datasheet
Download GS8342D09E-250 Datasheet




 GS8342D09E-250
Preliminary
GS8342D08/09/18/36Ew-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/167
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaQuad-II
Burst of 4 SRAM
167 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb
and 144Mb devices
SigmaQuadFamily Overview
The GS8342D08/09/18/36E are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342D08/18/36E SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342D08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B4 RAMs always transfer
data in four packets, A0 and A1 are internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfers. Because the LSBs are tied off internally,
the address field of a SigmaQuad-II B4 RAM is always two
address pins less than the advertised index depth (e.g., the 2M
x 18 has a 512K addressable index).
Parameter Synopsis
tKHKH
tKHQV
- 333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.50 ns
Rev: 1.02 8/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology




 GS8342D09E-250
Preliminary
GS8342D08/09/18/36E-333/300/250/200/167
www.DataSheet4U.com
1M x 36 SigmaQuad-II SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A
CQ
MCL/SA NC/SA
(256Mb) (72Mb)
W
BW2
K
BW1
R
SA
MCL/SA
(144Mb)
CQ
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30 Q21 D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30 D22 Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N
D34 D26 Q25 VSS SA
SA
SA
VSS Q10
D9
D1
P
Q35 D35 Q26
SA
SA
C
SA SA Q9 D0 Q0
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35
2. MCL = Must Connect Low
Rev: 1.02 8/2005
2/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology




 GS8342D09E-250
Preliminary
GS8342D08/09/18/36E-333/300/250/200/167
www.DataSheet4U.com
2M x 18 SigmaQuad-II SRAM—Top View
1 2 3 4 5 6 7 8 9 10
A
CQ
MCL/SA
(144Mb)
SA
W BW1 K
NC
R
SA
MCL/SA
(72Mb)
B NC Q9 D9 SA NC K BW0 SA NC NC
C NC NC D10 VSS SA NC SA VSS NC Q7
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD VDDQ NC
NC
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
Q4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
NC
M NC NC D16 VSS VSS VSS VSS VSS NC Q1
N NC D17 Q16 VSS SA SA SA VSS NC NC
P NC NC Q17 SA SA C SA SA NC D0
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. MCL = Must Connect Low
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.02 8/2005
3/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology






Recommended third-party GS8342D09E-250 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)