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SERIAL FLASH. MX25L512 Datasheet

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SERIAL FLASH. MX25L512 Datasheet






MX25L512 FLASH. Datasheet pdf. Equivalent




MX25L512 FLASH. Datasheet pdf. Equivalent





Part

MX25L512

Description

512K-BIT [x 1] CMOS SERIAL FLASH



Feature


MX25L512 www.DataSheet4U.com 512K-BIT [ x 1] CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface (SPI ) compatible -- Mode 0 and Mode 3 • 524,288 x 1 bit structure • 16 Equal Sectors with 4K byte each - Any Sect or can be erased individually • Sing le Power Supply Operation - 2.7 to 3. 6 volt for read, erase, and program ope rations • Latch-up protec.
Manufacture

Macronix International

Datasheet
Download MX25L512 Datasheet


Macronix International MX25L512

MX25L512; ted to 100mA from -1V to Vcc +1V PERFORM ANCE • High Performance - Fast acces s time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1 TTL Load) - Fast program time: 1.4ms(ty p.) and 5ms(max.)/page (256-byte per pa ge) - Fast erase time: 60ms(typ.) and 1 20ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/chip(512Kb) • Low Power Consumptio.


Macronix International MX25L512

n - Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(ma x.) at 33MHz - Low active programming c urrent: 15mA (max.) - Low active erase current: 15mA (max.) - Low standby curr ent: 10uA (max.) - Deep pow er-down mode 1uA (typical) • Minimum 100,000 erase/program cycles SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Block.


Macronix International MX25L512

Lock protection - The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions. • Auto Erase and Auto Program Algorithm program pulse w idths (Any page to be programed should have page in the erased state first) Status Register Feature • Electroni c Identification - RES command, 1-byt e Device ID HARDWARE FEA.

Part

MX25L512

Description

512K-BIT [x 1] CMOS SERIAL FLASH



Feature


MX25L512 www.DataSheet4U.com 512K-BIT [ x 1] CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface (SPI ) compatible -- Mode 0 and Mode 3 • 524,288 x 1 bit structure • 16 Equal Sectors with 4K byte each - Any Sect or can be erased individually • Sing le Power Supply Operation - 2.7 to 3. 6 volt for read, erase, and program ope rations • Latch-up protec.
Manufacture

Macronix International

Datasheet
Download MX25L512 Datasheet




 MX25L512
MX25L512
MX25L512
DATASHEET
The MX25L512 product family is not recommended for new designs. The MX25L512C
family is the recommended replacement. Please refer to MX25L512C datasheet for full
specifications and ordering information, or contact your local sales representative for
additional support.
P/N: PM1214
REV. 1.7, APR. 15, 2009
1




 MX25L512
MX25L512
512K-BIT [x 1] CMOS SERIAL FLASH
The MX25L512 product family is not recommended for new designs. The MX25L512C
family is the recommended replacement. Please refer to MX25L512C datasheet for full
specifications and ordering information, or contact your local sales representative for
additional support.
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
• 524,288 x 1 bit structure
• 16 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/chip(512Kb)
• Low Power Consumption
- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase in-
structions.
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1214
REV. 1.7, APR. 15, 2009
2




 MX25L512
Status Register Feature
Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-pin SOP (150mil)
- 8-USON (2x3mm)
- All Pb-free devices are RoHS Compliant
MX25L512
GENERAL DESCRIPTION
MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25L512
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is
enabled by CS# input.
MX25L512 provide sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the spec-
ified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and
erase command is executes on chip or sector (4K-bytes).
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC cur-
rent.
The MX25L512 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
P/N: PM1214
REV. 1.7, APR. 15, 2009
3






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