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QL3004E
PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Description
4/( S$6,& )3*$ 'DWD 6KHHW 8VDEOH 3/' *DWH S$6,& )3*$ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW\ 'HYLFH +LJKOLJKWV +LJK 3HUIRUPDQFH www.DataSheet4U.com 300 MHz 16-bit +LJK 'HQVLW\ )RXU /RZ6NHZ 'LVWULEXWHG 1HWZRUNV Two array clock/control networks available 4,000 Usable PLD Gates with 82 I/Os Counters, 400 MHz Datapaths 0.35...
QuickLogic Corporation
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