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CY7C1311AV18

Part Number	CY7C1311AV18
Manufacturer	Cypress Semiconductor
Description	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
Published	Dec 9, 2010
Detailed Description	PRELIMINARY CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb QDR™-II SRAM 4-Word Burst Architecture Features • Separate In...
Datasheet	CY7C1311AV18 PDF File

Overview

PRELIMINARY CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb QDR™-II SRAM 4-Word Burst Architecture Features • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high speed systems • Single multiplexed address input bus latches address inputs for both Read and Writ...

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CY7C1311AV18 (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture - Cypress Semiconductor

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