CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
Features
Separate Independent Read and Write data ports — Supports concurrent transactions 300-MHz clock for high bandwidth 4-Word Burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred...
