CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18
36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Separate independent read and write data ports — Supports concurrent transactions 300 MHz to 375 MHz clock for high bandwidth 4-Word Burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read ...
