CY7C1316AV18 CY7C1318AV18 CY7C1320AV18
18-Mbit DDR-II SRAM 2-Word Burst Architecture
Features
18-Mb density (2M x 8, 1M x 18, 512K x 36) 250-MHz clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz Two input clocks (K and K) for precise DDR timing — SRAM ...
