12-bit ADC. ADC1213S Datasheet

ADC1213S ADC. Datasheet pdf. Equivalent

ADC1213S Datasheet
Recommendation ADC1213S Datasheet
Part ADC1213S
Description Single 12-bit ADC
Feature ADC1213S; ADC1213S series Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface.
Manufacture NXP Semiconductors
Datasheet
Download ADC1213S Datasheet




NXP Semiconductors ADC1213S
ADC1213S series
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 1 — 14 March 2011
Product data sheet
1. General description
The ADC1213S is a single channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213S is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V source
for analog and a 1.8 V source for the output driver, it outputs data in serial mode via a
single differential lane, which complies with the JESD204A standard. The integration of
Serial Peripheral Interface (SPI) allows the user to easily configure the ADCs and the
serial output modes. The device also includes a programmable full-scale SPI to allow a
flexible input voltage range from 1 V (p-p) to 2 V (p-p).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213S ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
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„ SNR, 70 dBFS; SFDR, 86 dBc
„ Sample rates up to 125 Msps
„ Single channel, 12-bit pipelined ADC
core
„ 3 V, 1.8 V power supplies
„ Flexible input voltage range: 1 V (p-p)
to 2 V (p-p)
„ Serial output
„ Compliant with JESD204A serial
transmission standard
„ Pin compatible with ADC1613S series,
ADC1413S series, and ADC1113S125
„ Input bandwidth, 600 MHz
„ Power dissipation, 550 mW at 80 Msps
„ SPI register programming
„ Duty cycle stabilizer
„ High Intermediate Frequency (IF)
capability
„ Offset binary, two’s complement, gray
code
„ Power-down mode and Sleep mode
„ HVQFN32 package
3. Applications
„ Wireless and wired broadband
communications
„ Spectral analysis
„ Ultrasound equipment
„ Portable instrumentation
„ Imaging systems



NXP Semiconductors ADC1213S
NXP Semiconductors
ADC1213S series
Single 12-bit ADC; serial JESD204A interface
4. Ordering information
Table 1. Ordering information
Type number
Sampling
frequency
(Msps)
ADC1213S125HN/C1 125
ADC1213S105HN/C1 105
ADC1213S080HN/C1 80
ADC1213S065HN/C1 65
Package
Name
Description
Version
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; resin based;
body 7 × 7 × 0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; resin based;
body 7 × 7 × 0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; resin based;
body 7 × 7 × 0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; resin based;
body 7 × 7 × 0.8 mm
www.DataSheet4U.net
ADC1213S_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 March 2011
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors ADC1213S
NXP Semiconductors
5. Block diagram
ADC1213S series
Single 12-bit ADC; serial JESD204A interface
CLKP
CLKM
INP
INM
SDIO
SCLK
CS
SPI
SYNCP
SYNCN
DLL
PLL
T/H
INPUT
STAGE
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
12-BIT
PIPELINED
OTR
D11 to D0
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
8-bit 8-bit
10-bit
SERIALIZER A
OUTPUT
BUFFER A
CMLP
CMLN
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ADC1213S
Fig 1. Block diagram
ADC1213S_SER
Product data sheet
OTR
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
SENSE VDDD AGND
DGND VDDA
001aam776
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 March 2011
© NXP B.V. 2011. All rights reserved.
3 of 39







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