Binning compensation. CY8CLED08 Datasheet

CY8CLED08 compensation. Datasheet pdf. Equivalent

Part CY8CLED08
Description HB LED Controller Binning compensation
Feature CY8CLED08 EZ-Color™ HB LED Controller Features ■ HB LED Controller www.DataSheet4U.net ❐ Configurab.
Manufacture Cypress Semiconductor
Datasheet
Download CY8CLED08 Datasheet



CY8CLED08
CY8CLED08
EZ-Color™ HB LED Controller
Features
www.DHataBShLeEetD4UC.noetntroller
Configurable dimmers support up to Eight
independent LED channels
8- to 32- bits of resolution per channel
Dynamic reconfiguration enables LED controller plus other
features: CapSense®, Battery Charging, and Motor Control
Visual embedded design
LED-Based drivers
• Binning compensation
• Temperature feedback
• Optical feedback
• DMX512
PrISM modulation technology
Reduces radiated EMI
Reduces low frequency blinking
Powerful Harvard-architecture processor
M8C processor speeds to 24 MHz
3.0 to 5.25 V operating voltage
Operating voltages down to 1.0 V using
on-chip switch mode pump (SMP)
Industrial temperature range: –40 °C to +85 °C
Flexible on-chip memory
16 K flash program storage 50,000 erase/write cycles
256 bytes static random access memory (SRAM) data
storage
In-system serial programming (ISSP)
Partial flash updates
Flexible protection modes
EEPROM emulation in flash
Advanced peripherals (PSoC® blocks)
Eight digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse-width modulator
(PWMs)
• Up to two full-duplex universal asynchronous receiver
transmitter (UARTs)
• Multiple serial peripheral interface (SPI) masters or slaves
• Connectable to all general purpose I/O (GPIO) pins
12 Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 9-bit DACs
• Programmable gain amplifiers (PGA)
• Programmable filters and comparators
Complex peripherals by combining blocks
Programmable pin configurations
25 mA sink, 10 mA source on all GPIOs
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
Up to 12 analog inputs on GPIOs
Four 30 mA analog outputs on GPIOs
Configurable interrupt on all GPIOs
Complete development tools
Free development software
• PSoC Designer™
Full featured, in-circuit emulator (ICE) and programmer
Full speed emulation
Complex breakpoint structure
128 KB trace memory
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12981 Rev. *J
• San Jose, CA 95134-1709
•408-943-2600
Revised July 8, 2011



CY8CLED08
CY8CLED08
Logic Block Diagram
PSoC
CORE
Port 5
Port 4
Port 3
Port 2
Port 1
Port
0
Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
SRAM
256 Bytes
SROM Flash 16K
Interrupt
Controller
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
POR and LVD Internal
Decimator I2C
Voltage
System Resets Ref.
SYSTEM RESOURCES
Switch
Mode
Pump
Document Number: 001-12981 Rev. *J
Page 2 of 52





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