DatasheetsPDF.com

Luminance/Chroma Processor. CA3194 Datasheet

DatasheetsPDF.com

Luminance/Chroma Processor. CA3194 Datasheet






CA3194 Processor. Datasheet pdf. Equivalent




CA3194 Processor. Datasheet pdf. Equivalent





Part

CA3194

Description

Single Chip PAL Luminance/Chroma Processor



Feature


www.DataSheet.co.kr Semiconductor May 1997 NOT RE ME COM DF NDE OR NE ES WD IGN S CA3194 Single Chip PAL L uminance/Chroma Processor Features • All PAL Luminance and Chrominance Proc essing Circuitry on a Single Chip in a 24-Lead Plastic Package • Phase-Locke d Subcarrier Regeneration Utilizing Sam ple-and-Hold • DC Controls for Bright ness, Contrast, and Colo.
Manufacture

Intersil

Datasheet
Download CA3194 Datasheet


Intersil CA3194

CA3194; r Saturation Functions • Input for Ave rage Beam-Current Limiting • Contrast Control Having Excellent Tracking of L uma and Chroma Channels • Low-lmpedan ce RGB Outputs with Excellent Tracking for Direct Coupling to Video Driver Cir cuitry Description The Harris CA3194E is a silicon monolithic integrated circ uit designed to perform all of the sign al processing functions .


Intersil CA3194

for both the chroma and luminance signal s of PAL color television receivers. Th is circuit performs all the functions n eeded between the video detector and th e video RGB output stages. DC contrast, brightness, and saturation controls an d average beam limiting functions are i ncluded. The RGB buffer stages are capa ble of delivering 5mA of current into t he video output st.


Intersil CA3194

ages. NOTE: Formerly Dev. No. TA10313. Ordering Information PART NUMBER CA3194 E TEMPERATURE RANGE -40oC to +85oC PACK AGE 24 Lead PDIP Pinout CA3194 (PDIP) TOP VIEW GND 1 CHROMA OUT 2 SAT. CONTR. 3 CHROMA INPUT 4 ACC FILTER 5 ACC FILT ER 6 APC FILTER 7 APC FILTER 8 90o INPU T 9 0o INPUT 10 VCO OUTPUT 11 VCC 12 AV ER. BEAM 24 INFO 23 BRIGHTNESS CONTROL 22 PICTURE CONTROL.

Part

CA3194

Description

Single Chip PAL Luminance/Chroma Processor



Feature


www.DataSheet.co.kr Semiconductor May 1997 NOT RE ME COM DF NDE OR NE ES WD IGN S CA3194 Single Chip PAL L uminance/Chroma Processor Features • All PAL Luminance and Chrominance Proc essing Circuitry on a Single Chip in a 24-Lead Plastic Package • Phase-Locke d Subcarrier Regeneration Utilizing Sam ple-and-Hold • DC Controls for Bright ness, Contrast, and Colo.
Manufacture

Intersil

Datasheet
Download CA3194 Datasheet




 CA3194
www.DataSheet.co.kr
Semiconductor
May 1997
Features
CA3194
NOT
RECOMMENDED
FOR
NEW
DESIGNS
Single Chip PAL
Luminance/Chroma Processor
Description
• All PAL Luminance and Chrominance Processing The Harris CA3194E is a silicon monolithic integrated circuit
Circuitry on a Single Chip in a 24-Lead Plastic designed to perform all of the signal processing functions for both
Package
the chroma and luminance signals of PAL color television receivers.
• Phase-Locked Subcarrier Regeneration Utilizing
Sample-and-Hold
• DC Controls for Brightness, Contrast, and Color
Saturation Functions
• Input for Average Beam-Current Limiting
• Contrast Control Having Excellent Tracking of
Luma and Chroma Channels
• Low-lmpedance RGB Outputs with Excellent
Tracking for Direct Coupling to Video Driver
Circuitry
This circuit performs all the functions needed between the video
detector and the video RGB output stages. DC contrast, bright-
ness, and saturation controls and average beam limiting functions
are included. The RGB buffer stages are capable of delivering
5mA of current into the video output stages.
NOTE: Formerly Dev. No. TA10313.
Ordering Information
PART
NUMBER
CA3194E
TEMPERATURE
RANGE
-40oC to +85oC
PACKAGE
24 Lead PDIP
Pinout
CA3194
(PDIP)
TOP VIEW
GND 1
CHROMA OUT 2
SAT. CONTR. 3
CHROMA INPUT 4
ACC FILTER 5
ACC FILTER 6
APC FILTER 7
APC FILTER 8
90o INPUT 9
0o INPUT 10
VCO OUTPUT 11
VCC 12
AVER. BEAM
24 INFO
23
BRIGHTNESS
CONTROL
22 PICTURE CONTROL
21
LOW PASS
FILTER
20 LUMA INPUT
19
PEAK BEAM
LEVEL
18 R OUTPUT
17 G OUTPUT
16 B OUTPUT
15 VR-Y INPUT
14 VB-Y INPUT
13 SANDCASTLE
TERMINAL VOLTAGE AND CURRENT RATINGS
VOLTAGE (NOTE 1) -V
CURRENT - mA
TERMINAL MIN MAX IIN IOUT
1 ----
2 0 13 0 30
3 0 8 10 -
4 05 - -
5
0 Note -
-
6 - - 0.1 0.5
7
0 Note -
-
8
0 Note -
-
9 08 - -
10 0 8 - 0.7
11 0 13 - 10
12
0 13 -
-
13
0 12 -
-
14 0 5 - 1.5
15 0 5 - 1.5
16 0 13 - 10
17 0 13 - 10
18 0 13 - 10
19
0 Note -
-
20 0 5 - -
21
0 Note -
-
22 0 8 - -
23 0 5 - -
24
NOTE:
0 12 -
-
1. The maximum should not exceed the VCC voltage. Voltage with respect to
Terminal 1 for VCC (Terminal 12) of 12V ±10%.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
7-56
File Number 1270.3
Datasheet pdf - http://www.DataSheet4U.net/




 CA3194
www.DataSheet.co.kr
Specifications CA3194
Absolute Maximum Ratings
Operating Conditions
Supply Voltage and Current
Pin 12 Voltage Range . . . . . . . . . . . . . . . . 11V (Min) to 13V (Max)
Pin 12 Current Range . . . . . . . . . . . . . 44mA (Typ) to 60mA (Max)
Power Dissipation
Up to TA = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825mW
Above TA = +25oC. . . . . . . . . . . . . . . . Derate Linearly 8.7mW/oC
Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Package Characteristics (oC/W)
θJA
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications TA = +25oC, VCC = 12V, VS = 2.85V, VC = 2.85V, VAB = VPB = VCC, VB adjusted for V18 = 6.3V, CX adjusted
for FOSC = 4.43361875MHz, Sandcastle: VBG = 8.0V, VBLANK = 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit
PARAMETER
LUMINANCE SECTION
Input Impedance (Terminal 20)
Luminance Channel Input Voltage
Bandwidth of Luminance Channel
Brightness Control Range (Terminal 23)
Output Black Level
Range
Offset
Contrast Control Range (Terminal 22)
Luminance Gain Control Range
RGB Output Swing
CHROMlNANCE SECTION
Input Impedance (Terminal 4)
Chroma Channel Input Voltage
ACC Range
Input Burst Level for Kill (Note 1)
Contrast Control Chroma/Luma Tracking
TEST CONDITIONS
TYPICAL
VALUE
UNITS
Luma Input Signal = 30% Sync.
Luma Input Signal: 0.5VP-P (30% Sync) modulated CW
Adj. modulation frequency for -3dB at color outputs.
For Control Characteristics, See Figures 1 and 2.
Luma Input Signal: 0.5VP-P (30% Sync)
VB 0V - 5V,Measured at Pin 18 black level.
See Figures 1 and 2.
Luminance Input: 0.5VP-P (30% Sync), for Control Characteristics.
See Figure 3
Luminance Input: 0.5VP-P (30% Sync), VC = 0.5V - 5V measure
Pin 18 black level to maximum white level. See Figure 4.
Luminance Input: 0.5VP-P (30% Sync), VC = 5V, read black
level to peak white. See Figures 5 and 6.
6
5
0.5
8
0 - 3.5
5.9-9.7
0.6 Max.
0-5
32
4
k
pF
VP-P
MHz
VDC
VDC
VDC
VDC
dB
VP-P
See Figures 7 and 8.
4.5
5
Chroma
220
Burst
100
+6 - (-20)
Adjust chroma input Pin 4 until Pin 2 25mVP-P.
Measure Burst level at Pin 4.
10
Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P.
Luminance Input: 0.35VP-P, VS adjusted for Chroma at
Pin 18 = 2VP-P. VC is adjusted for luminance at Pin 18 = 2VP-P,
VC is again adjusted for luminance of +6 and -9dB.
Then read chroma percentage difference. See Figure 9.
±5
k
pF
mVP-P
mVP-P
dB
mVP-P
%
7-57
Datashe




 CA3194
www.DataSheet.co.kr
Specifications CA3194
Electrical Specifications TA = +25oC, VCC = 12V, VS = 2.85V, VC = 2.85V, VAB = VPB = VCC, VB adjusted for V18 = 6.3V, CX adjusted
for FOSC = 4.43361875MHz, Sandcastle: VBG = 8.0V, VBLANK = 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit (Continued)
PARAMETER
TEST CONDITIONS
Saturation Control Range (Terminal 3)
For control characteristic, see Figure 10.
Maximum Chroma Output Voltage (Terminal 2) Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P.
Adjust VC and VS for maximum Pin 2 output.
OSCILLATOR SECTION
Pull-In Range
Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P.
Adjust CX for HI/LO fOSC without Chroma signal.
Apply signal to lock.
Static Phase Error
TYPICAL
VALUE
0-5
2.5
±500
2
DEMODULATOR SECTION
R-Y Demodulator Conversion Gain
Chroma Input: Burst =100mV, Chroma = 220mVP-P,Vø.
Adjust VC for V18 = 1V. Read V15. Calculate V18/V15.
B-Y Demodulator Conversion Gain
Chroma Input: Burst = 100mVP-P, Uø. Read V16 and V14.
Calculate V16/V14. VC remains as for R-Y gain.
G-Y/B-Y Matrix Ratio
Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Uø
read V17 and V16, Calculate V17/V16. VC remains as above.
G-Y/R-Y Matrix Ratio
Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Vø.
Read V17 and V18. Calculate V17/V18. VC remains as above.
Sub-Carrier and Harmonic Content at Outputs No Chroma or Luma Input. Read residual carrier at outputs.
10
18
0.2
0.5
30
SANDCASTLE PULSE
Horizontal and Vertical Blanking Pedestal
2-5
Burst Gate Pulse
NOTES:
1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17.
2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals.
3. The reference voltage can be adjusted by changing the values of the voltage divider.
6.5 - VCC
UNITS
VDC
VP-P
Hz
Deg./
100Hz
Ratio
Ratio
Ratio
Ratio
mVP-P
V
V
Circuit Description (See Block Diagram and Figure 20)
The chroma signal is externally separated from the video
signal by means of a bandpass or high-pass filter and
applied to pin 4. The burst is separated in the first chroma
stage and applied to the synchronous detector which pro-
vides information to sample-and-hold circuits for APC
(phase-locked loop), ACC (automatic chroma gain control)
and identification and killing. The 4.43MHz crystal oscillator
is phase-locked to the burst and provides 0 degrees and 90
degrees (via an external phase shifter) carriers to the
chroma demodulators. The burst and chroma amplitude at
the output of the first chroma amplifier is kept constant by
the automatic gain control.
A buffer stage drives the external PAL delay line. The sepa-
rated U and V signals are applied to pins 14 and 15, respec-
tively, and demodulated. A standard G-Y matrix is included
on the chip.
The luminance signal passes through the subcarrier trap
and through the luminance delay line and enters the chip at
pin 20. Contrast and brightness control is provided before
the luminance signal is combined with the color difference
signals in the Y matrix. Average and peak beam limiting cir-
cuits are controlled from pins 24 and 19.
The second chroma stage provides saturation control (pin 3)
which tracks the contrast control in the luminance channel.
This stage is also used for color killing.
7-58
Datasheet pdf - http://www.DataSheet4U.net/






Recommended third-party CA3194 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)