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AK8856

AKM
Part Number AK8856
Manufacturer AKM
Description NTSC/PAL Digital Video Decoder
Published Feb 20, 2014
Detailed Description ASAHI KASEI [ AK8856 ] AK8856 NTSC/PAL Digital Video Decoder General Description The AK8856 decodes NTSC or PAL compos...
Datasheet PDF File AK8856 PDF File

AK8856
AK8856

Overview
ASAHI KASEI [ AK8856 ] AK8856 NTSC/PAL Digital Video Decoder General Description The AK8856 decodes NTSC or PAL composite video signals into digital video data.
The outputs are ITU-R BT.
601 level compatible Y, Cb and Cr signals.
The decoded result is scaled to 601, VGA (interlaced output), CIF, QVGA, QCIF, rotated QVGA , or rotated CIF(progressive).
Information including closed caption, VBID, and WSS are encoded in the video signal can be read out externally.
The AK8856 is controlled by through an I2C interface.
Features • • • • • • • • NTSC-M, NTSC-4.
43 / PAL- B, D, G, H, I, N, Nc, M, 60 composite signal decoding process 10 Bit ADC (sampling at 24.
5454MHz or 27MHz) Integrated PGA (0dB ~ 12dB) Automatic color control (ACC) function Adaptive automatic gain control (AGC) function 1D or 2D YC separation Phase compensation for PAL Output interface - ITU-R BT.
656 output format (4:2:2 8-bit parallel output with EAV / SAV) - Camera interface - Interface with HD / VD / DVALID signals Closed caption decoding function (read by register setting) VBID (CGMS-A) decoding function (CRCC decode) (read by register setting) WSS decoding function (read by register setting) Macrovision signal detect function Power-down function 2-channel analog input selector I2C control compatible Core voltage (AVDD, DVDD) 1.
65 - 1.
8V I/O voltage (PVDD) 1.
65 - 3.
3V (AK8856VG) / 1.
65 - 3.
6V (AK8856VN) Package: 41 FBGA 4.
0mm x 4.
0mm / 48 QFN 7.
2mm x 7.
2mm • • • • • • • • • • * The output that meets the ITU-R BT.
656 standard according to the fineness of the input signal might not be available.
Rev-01 1 2007/03 Free Datasheet http://www.
datasheet-pdf.
com/ ASAHI KASEI [ AK8856 ] Block Diagram XTI XTO LPF SCL SDA PDN RSTN OE 27MHz Clock GEN PLL 27MHz -> 27.
0000MHz or 24.
5454MHz 27 or 24.
5454MHz I2C bus uC Interface Register DATA[7:0] HD/HV Output Buffer VD/VAF/FIELD DVALID NSIG DTCLK AIN1 AIN2 MUX CLAMP PGA 10-bit ADC CLKMOD Decimation Filter SYNC-Separation AGC Ctrl VBI Info Timing Control...


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