NAND gate. HEF4068B Datasheet

HEF4068B gate. Datasheet pdf. Equivalent

HEF4068B Datasheet
Recommendation HEF4068B Datasheet
Part HEF4068B
Description 8-input NAND gate
Feature HEF4068B; INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS H.
Manufacture NXP
Datasheet
Download HEF4068B Datasheet




NXP HEF4068B
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4068B
gates
8-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995



NXP HEF4068B
Philips Semiconductors
8-input NAND gate
DESCRIPTION
The HEF4068B provides the 8-input NAND function. The
outputs are fully buffered for highest noise immunity and
pattern insensitivity of output impedance.
Product specification
HEF4068B
gates
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4068BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4068BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4068BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram.
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2



NXP HEF4068B
Philips Semiconductors
8-input NAND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL TYP.
MAX.
Propagation delays
In O
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
95 195
40 85
30 65
80 165
35 70
30 60
60 120
30 60
20 40
60 120
30 60
20 40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Product specification
HEF4068B
gates
TYPICAL EXTRAPOLATION
FORMULA
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
53 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
700 fi + ∑(foCL) × VDD2
where
10
2900 fi + ∑(foCL) × VDD2
fi = input freq. (MHz)
15
7200 fi + ∑(foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3







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