95V857 Datasheet: ICS95V857





95V857 ICS95V857 Datasheet

Part Number 95V857
Description ICS95V857
Manufacture Integrated Circuit Systems
Total Page 13 Pages
PDF Download Download 95V857 Datasheet PDF

Features: Integrated Circuit Systems, Inc. ICS95V 857 2.5V Wide Range Frequency Clock Dr iver (45MHz - 233MHz) Recommended Appli cation: • DDR Memory Modules / Zero D elay Board Fan Out • Provides complet e DDR registered DIMM solution with ICS SSTVF16857, ICSSSTVF16859 or ICSSSTV328 52 Product Description/Features: • Lo w skew, low jitter PLL clock driver • 1 to 10 differential clock distributio n (SSTL_2) • Feedback pins for input to output synchronization • PD# for p ower management • Spread Spectrum-tol erant inputs • Auto PD when input sig nal removed Specifications: • Meets P C3200 Class A+ specification for DDR-I 400 support • Covers all DDRI speed g rades Switching Characteristics: • CY CLE - CYCLE jitter: <50ps • OUTPUT - OUTPUT skew: <40ps • Period jitter: 30ps Pin Configuration GND CLKC0 CLKT 0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 V DD VDD CLK_INT CLK_INC VDD AVDD AGND GN D CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38.

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Integrated
Circuit
Systems, Inc.
ICS95V8 5 7
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
• DDR Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR registered DIMM solution
with ICSSSTVF16857, ICSSSTVF16859 or
ICSSSTV32852
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum-tolerant inputs
• Auto PD when input signal removed
Specifications:
• Meets PC3200 Class A+ specification for DDR-I 400
support
• Covers all DDRI speed grades
Switching Characteristics:
• CYCLE - CYCLE jitter: <50ps
• OUTPUT - OUTPUT skew: <40ps
• Period jitter: ±30ps
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 PD#
36 FB_INT
35 FB_INC
34 VDD
33 FB_OUTC
32 FB_OUTT
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
48-Pin TSSOP/TVSOP
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
Block Diagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND H
L
H LH L
H Bypassed/off
GND
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
H
L
L
H
H
X
HL
LH
HL
LH
HL
<20MHz)(1)
HL
ZZ
ZZ
LH
HL
ZZ
H
Z
Z
L
H
Z
L Bypassed/off
Z off
Z off
H on
L on
Z off
PD#
FB_INT
FB_INC
CLK_INC
CLK_INT
Control
Logic
PLL
0674U01/27/09
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
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