Flash Memory. AT49F001AT Datasheet

AT49F001AT Datasheet PDF, Equivalent


Part Number

AT49F001AT

Description

Flash Memory

Manufacture

Atmel

Total Page 18 Pages
PDF Download
Download AT49F001AT Datasheet


AT49F001AT Datasheet
Features
Single-voltage Operation
– 5V Read
– 5V Reprogramming
Fast Read Access Time – 45 ns
Internal Program Control and Timer
Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Two Main Memory Blocks (32K Bytes, 64K Bytes)
Fast Erase Cycle Time – 3 Seconds
Byte-by-Byte Programming – 30 µs/Byte Typical
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
– 20 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
1-megabit
(128K x 8)
5-volt Only
Flash Memory
Description
The AT49F001A(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its
1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
45 ns with power dissipation of just 110 mW over the industrial temperature range.
Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
RESET
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
RESET
Data Inputs/Outputs
No Connect
PLCC Top View
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
A11
A9
A8
A13
A14
NC
WE
VCC
* RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
AT49F001A
AT49F001AN
AT49F001AT
AT49F001ANT
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
Note: *This pin is a NC on the AT49F001AN(T)
3365C–FLASH–9/03
1
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AT49F001AT Datasheet
Block Diagram
VCC
GND
OE
WE
CE
RESET
ADDRESS
INPUTS
When the device is deselected, the CMOS standby current is less than 50 µA. For the
AT49F001AN(T), pin 1 for the PLCC package and pin 9 for the TSOP package are no connect
pins.
To allow for simple in-system reprogrammability, the AT49F001A(N)(T) does not require high
input voltages for programming. Five-volt-only commands determine the read and program-
ming operation of the device. Reading data out of the device is similar to reading from an
EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the
AT49F001A(N)(T) is performed by erasing a block of data and then programming on a byte by
byte basis. The byte programming time is a fast 30 µs. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the end of a byte program cycle has
been detected, a new access for a read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device internally con-
trols the erase operations. There are two 8K byte parameter block sections, two main memory
blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is enabled by a
command sequence. The 16K-byte boot block section includes a reprogramming lock out fea-
ture to provide data integrity. The boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected from being reprogrammed.
In the AT49F001A(N)(T), once the boot block programming lockout feature is enabled, the
contents of the boot block are permanent and cannot be changed. In the AT49F001A(T), once
the boot block programming lockout feature is enabled, the contents of the boot block cannot
be changed with input voltage levels of 5.5 volts or less.
CONTROL
LOGIC
Y DECODER
X DECODER
AT49F001A(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
MAIN MEMORY
BLOCK 2
(64K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
AT49F001A(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
BOOT BLOCK
(16K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
1FFFF
1C000
1BFFF
1A000
19FFF
18000
17FFF
10000
0FFFF
00000
2 AT49F001A(N)(T)
3365C–FLASH–9/03
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