SAM9G45 Embedded MPU Datasheet

SAM9G45 Datasheet, PDF, Equivalent


Part Number

SAM9G45

Description

AT91SAM ARM-based Embedded MPU

Manufacture

ATMEL

Total Page 30 Pages
Datasheet
Download SAM9G45 Datasheet


SAM9G45
AT91SAM ARM-based Embedded MPU
SAM9G45
DATASHEET
Description
The ARM926EJ-S based SAM9G45 features the frequently demanded combination of user interface function-
ality and high data rate connectivity, including LCD Controller, resistive touch-screen, camera interface, audio,
Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400 MHz and multiple 100+
Mbps data rate peripherals, the SAM9G45 has the performance and bandwidth to the network or local storage
media to provide an adequate user experience.
The SAM9G45 supports DDR2 and NAND Flash memory interfaces for program and data storage. An internal
133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and dis-
tributed memory including a 64-Kbyte SRAM which can be configured as a tightly coupled memory (TCM)
sustains the high bandwidth required by the processor and the high speed peripherals.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and
peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it sup-
ports 0.8 ball pitch package for low cost PCB manufacturing.
The SAM9G45 power management controller features efficient clock gating and a battery backup section min-
imizing power consumption in active and standby modes.
6438KATARM12-Feb-13
http://www.Datasheet4U.com

SAM9G45
1. Features
400 MHz ARM926EJ-S™ ARM® Thumb® Processor
– 32 Kbytes Data Cache, 32 Kbytes Instruction Cache, MMU
Memories
– DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR
– External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND
Flash with ECC
– One 64-Kbyte internal SRAM, single-cycle access at system speed or processor speed through TCM interface
– One 64-Kbyte internal ROM, embedding bootstrap routine
Peripherals
– LCD Controller supporting STN and TFT displays up to 1280*860
– ITU-R BT. 601/656 Image Sensor Interface
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with On-Chip Transceiver
– 10/100 Mbps Ethernet MAC Controller
– Two High Speed Memory Card Hosts (SDIO, SDCard, MMC)
– AC'97 controller
– Two Master/Slave Serial Peripheral Interfaces
– Two Three-channel 16-bit Timer/Counters
– Two Synchronous Serial Controllers (I2S mode)
– Four-channel 16-bit PWM Controller
– Two Two-wire Interfaces
– Four USARTs with ISO7816, IrDA, Manchester and SPI modes
– 8-channel 10-bit ADC with 4-wire Touch Screen support
– Write Protected Registers
System
– 133 MHz twelve 32-bit layer AHB Bus Matrix
– 37 DMA Channels
– Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash
– Reset Controller with on-chip Power-on Reset
– Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators
– Internal Low-power 32 kHz RC Oscillator
– One PLL for the system and one 480 MHz PLL optimized for USB High Speed
– Two Programmable External Clock Signals
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock
I/O
– Five 32-bit Parallel Input/Output Controllers
– 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input
Package
– 324-ball TFBGA, pitch 0.8 mm
SAM9G45 [DATASHEET]
6438KATARM12-Feb-13
2


Features AT91SAM ARM-based Embedded MPU SAM9G45 D ATASHEET Description The ARM926EJ-S ba sed SAM9G45 features the frequently dem anded combination of user interface fun ctionality and high data rate connectiv ity, including LCD Controller, resistiv e touch-screen, camera interface, audio , Ethernet 10/100 and high speed USB an d SDIO. With the processor running at 4 00 MHz and multiple 100+ Mbps data rate peripherals, the SAM9G45 has the perfo rmance and bandwidth to the network or local storage media to provide an adequ ate user experience. The SAM9G45 suppor ts DDR2 and NAND Flash memory interface s for program and data storage. An inte rnal 133 MHz multi-layer bus architectu re associated with 37 DMA channels, a d ual external bus interface and distribu ted memory including a 64-Kbyte SRAM wh ich can be configured as a tightly coup led memory (TCM) sustains the high band width required by the processor and the high speed peripherals. The I/Os suppo rt 1.8V or 3.3V operation, which are independently configurable.
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