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ECC SO-UDIMM. SGN04G72G2BQ2SA-CCRT Datasheet

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ECC SO-UDIMM. SGN04G72G2BQ2SA-CCRT Datasheet






SGN04G72G2BQ2SA-CCRT SO-UDIMM. Datasheet pdf. Equivalent




SGN04G72G2BQ2SA-CCRT SO-UDIMM. Datasheet pdf. Equivalent





Part

SGN04G72G2BQ2SA-CCRT

Description

204 Pin ECC SO-UDIMM



Feature


Data Sheet Rev.1.0 28.11.2013 4096MB DDR3 – SDRAM ECC SO-DIMM 204 Pin ECC SO-UDIMM SGN04G72G2BQ2SA-xx(E/W)RT 4GBy te in FBGA Technology RoHS compliant Fe atures:       204-pin 72-bit DDR3 Small Outline, Dual-In-Lin e Double Data Rate synchronous DRAM Mod ule Module organization: dual rank 512M x 72 VDD = 1.5V ±0.075V, VDDQ 1.5V ± 0.075V 1.5V I/O ( SSTL_15 compatib.
Manufacture

Swissbit

Datasheet
Download SGN04G72G2BQ2SA-CCRT Datasheet


Swissbit SGN04G72G2BQ2SA-CCRT

SGN04G72G2BQ2SA-CCRT; le) Fly-by-bus with termination for C/A & CLK bus 2 On-board I C temperature se nsor with integrated serial presence-de tect (SPD) EEPROM This module is fully pin and functional compatible to the JE DEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM design spec. and JEDEC- Standard MO-268 . (see www.jedec.org) The pcb and all c omponents are manufactured according to the RoHS complian.


Swissbit SGN04G72G2BQ2SA-CCRT

ce specification [EU Directive 2002/95/E C Restriction of Hazardous Substances ( RoHS)] DDR3 - SDRAM component Samsung K 4B2G0846Q 256Mx8 DDR3 SDRAM in PG-TFBGA -78 package 8-bit prefetch architecture Programmable CAS Latency, CAS Write La tency, Additive Latency, Burst Length a nd Burst Type. On-Die-Termination (ODT) and Dynamic ODT for improved signal in tegrity. Refresh, .


Swissbit SGN04G72G2BQ2SA-CCRT

Self Refresh and Power Down Modes. ZQ Ca libration for output driver and ODT. Sy stem Level Timing Calibration Support v ia Write Leveling and Multi Purpose Reg ister (MPR) Read Pattern. Options:  Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1600 MT/s CL11 Module density 409 6MB with 18 dies and 2 rank Standard Gr ade Grade E Grade W (TA) (TC) (TA) (TC) (TA) (TC) 0°C to 70.

Part

SGN04G72G2BQ2SA-CCRT

Description

204 Pin ECC SO-UDIMM



Feature


Data Sheet Rev.1.0 28.11.2013 4096MB DDR3 – SDRAM ECC SO-DIMM 204 Pin ECC SO-UDIMM SGN04G72G2BQ2SA-xx(E/W)RT 4GBy te in FBGA Technology RoHS compliant Fe atures:       204-pin 72-bit DDR3 Small Outline, Dual-In-Lin e Double Data Rate synchronous DRAM Mod ule Module organization: dual rank 512M x 72 VDD = 1.5V ±0.075V, VDDQ 1.5V ± 0.075V 1.5V I/O ( SSTL_15 compatib.
Manufacture

Swissbit

Datasheet
Download SGN04G72G2BQ2SA-CCRT Datasheet




 SGN04G72G2BQ2SA-CCRT
Data Sheet
Rev.1.0 28.11.2013
4096MB DDR3 SDRAM ECC SO-DIMM
204 Pin ECC SO-UDIMM
SGN04G72G2BQ2SA-xx(E/W)RT
4GByte in FBGA Technology
RoHS compliant
Options:
Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1600 MT/s CL11
Marking
-CC
-DC
Module density
4096MB with 18 dies and 2 rank
Standard Grade
Grade E
Grade W
(TA) 0°C to 70°C
(TC) 0°C to 85°C
(TA) 0°C to 85°C
(TC) 0°C to 95°C
(TA) -40°C to 85°C
(TC) -40°C to 95°C
*) The refresh rate has to be doubled when 85°C<TC<95°C
Environmental Requirements:
Operating temperature (ambient)
Standard Grade
0°C to 70°C
E-Grade
0°C to 85°C
W-Grade
-40°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double
Data Rate synchronous DRAM Module
Module organization: dual rank 512M x 72
VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V
1.5V I/O ( SSTL_15 compatible)
Fly-by-bus with termination for C/A & CLK bus
On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
This module is fully pin and functional compatible to the
JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM
design spec. and JEDEC- Standard MO-268. (see
www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR3 - SDRAM component Samsung K4B2G0846Q
256Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit prefetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
Refresh, Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
Figure: mechanical dimensions1
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
1if no tolerances specified ± 0.15mm
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 17




 SGN04G72G2BQ2SA-CCRT
Data Sheet
Rev.1.0 28.11.2013
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line
Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses
internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to
achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ
and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. The burst length is either four or
eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated
at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent
operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-
down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
512M x 72bit
DDR3 SDRAMs used
18 x 256M x 8bit (2Gbit)
Row
Addr.
15
Device Bank
Addr.
Column
Addr.
Refresh
Module
Bank Select
BA0, BA1, BA2 10
8k S0#, S1#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
Module Density Transfer Rate Clock Cycle/Data bit rate
SGN04G72G2BQ2SA-CC[E/W]RT
4GByte
10.6 GB/s
1.5ns/1333MT/s
SGN04G72G2BQ2SA-DC[E/W]RT
4GByte
12.8 GB/s
1.25ns/1600MT/s
Latency
9-9-9
11-11-11
Pin Name
A0 A9, A11 A14
A10/AP
BA0 BA2
DQ0 DQ63
CB0 CB07
DM0 DM8
DQS0 DQS8
DQS0# DQS8#
RAS#
CAS#
WE#
CKE0 CKE1
S0#, S1#
CK0 CK1
CK0# CK1#
VDD
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
ECC check bits
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Chip Select
Clock Inputs, positive line
Clock Inputs, negative line
Supply Voltage (1.5V± 0.075V)
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 17




 SGN04G72G2BQ2SA-CCRT
Data Sheet
Rev.1.0 28.11.2013
VREFDQ
VREFCA
VSS
VTT
VDDSPD
SCL
SDA
SA0 SA1
ODT0, ODT1
Event#
NC
Reference voltage: DQ, DM (VDD/2)
Reference voltage: Control, command, and address (VDD/2)
Ground
Termination voltage: Used for control, command, and address (VDD/2).
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
No Connection
Pin Configuration
Frontside
PIN Symbol PIN Symbol PIN
1
VREFDQ
53
VSS 103
3
VSS
55
DQ24
105
5
DQ0
57
DQ25
107
7
DQ1
59
DM3
109
9 VSS 61 VSS 111
11
DM0
63
DQ26
113
13
DQ2
65
DQ27
115
15 DQ3 67
VSS 117
17 VSS 69 CB0 119
19 DQ8 71 CB1 121
21 DQ9 Key 123
23 VSS 73 VSS 125
25
DQS1#
75
DQS8#
127
27
DQS1
77
DQS8
129
29 VSS 79 VSS 131
31 DQ10 81
CB2 133
33 DQ11 83
CB3 135
35 VSS 85 VDD 137
37
DQ16
87
CKE0
139
39
DQ17
89
CKE1
141
41 VSS 91 BA2 143
43 DQS2# 93
VDD 145
45
DQS2
95
A12/BC#
147
47 VSS 97 A8 149
49 DQ18 99
A5 151
51
DQ19
101
VDD
153
Signal in brackets may be routed to the socket connector, but is not used on the module
Symbol
A3
A1
A0
VDD
CK0
CK0#
VDD
A10/AP
BA0
WE#
VDD
CAS#
S0#
S1#
VDD
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
PIN
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Symbol
VSS
DM5
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 17



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