Sensing MCU. C8051F971 Datasheet

C8051F971 MCU. Datasheet pdf. Equivalent

Part C8051F971
Description Low Power Capacitive Sensing MCU
Feature C8051F97x Low Power Capacitive Sensing MCU with up to 32 kB of Flash Low Power Consumption - 200 µA/.
Manufacture Silicon Laboratories
Datasheet
Download C8051F971 Datasheet



C8051F971
C8051F97x
Low Power Capacitive Sensing MCU with up to 32 kB of Flash
Low Power Consumption
- 200 µA/MHz in active mode (24.5 MHz clock)
- 2 µs wakeup time
- 55 nA sleep mode with brownout detector
- 280 nA sleep mode with LFO
- 600 nA sleep mode with external crystal
Capacitance Sense Interface
- Supports buttons, sliders, wheels, and proximity sensing
- Fast 40 µs per channel conversion time
- 16-bit resolution, up to 43 input channels
- Auto scan and wake-on-touch
- Auto-accumulate up to 64x samples
10-Bit Analog-to-Digital Converter
- Up to 43 external pin input channels, up to 300 ksps
- Internal VREF or external VREF supported
Clock Sources
- Internal oscillators: 24.5 MHz, ±2% accuracy supports UART
operation; 20 MHz low power oscillator requires very little bias
current.
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or internal LFO
- Can switch between clock sources on-the-fly; useful in imple-
menting various power-saving modes
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive in-
system debug (no emulator required)
- Provides breakpoints, single stepping, inspect/modify memory
and registers
Unique Identifier
- 128-bit unique key for each device
High-Speed CIP-51 µC Core
- Efficient, pipelined instruction architecture
- Up to 25 MIPS throughput with 25 MHz clock
- Uses standard 8051 instruction set
- Expanded interrupt handler
- 1-cycle 16 x 16 MAC Engine
- 7-channel Direct Memory Access (DMA) module
Memory
- Up to 32 kB flash
- Flash is in-system programmable in 512-Byte sectors
- Up to 8 kB RAM
General-Purpose I/O
- Up to 43 pins with high sink current and programmable drive
- Crossbar-enabled
Timer/Counters and PWM
- 4 general purpose 16-bit timer/counters
- 16-bit Programmable Counter Array (PCA) with three channels
of PWM, capture/compare, or frequency output capability, and
watchdog timer
Supply Voltage: 1.8 to 3.6 V
- Built-in LDO regulator allows a high analog supply voltage and
low digital core voltage
- 2 supply monitors (brownout detector) for sleep and active
modes
Package Options
- 24-pin QFN (4x4 mm)
- 32-pin QFN (5x5 mm)
- 48-pin QFN (6x6 mm)
Temperature Ranges: –40 to +85 °C
Core / Memory / Support
16-32 kB Flash
4-8 kB RAM
CIP-51
(25 MHz)
Core LDO
Supply Monitor
16-bit CRC
7 ch. DMA 16 x 16 MAC
C2 Serial Debug / Programming
Digital Peripherals
UART
I2C / SMBus HS I2C Slave
SPI
4 x 16-bit Timers
3-Channel PCA / Watchdog
Clocking / Oscillators
24.5 MHz Precision Oscillator
20 MHz Low Power Oscillator
smaRTClock with 16.4 kHz LFO
External Oscillator
Analog Peripherals
SAR ADC (10-bit 300 ksps)
Capacitive Sensing
Voltage Reference
Temperature Sensor
Rev 1.1 12/16
Copyright © 2016 by Silicon Laboratories
C8051F97x



C8051F971
1. Electrical Characteristics .................................................................................................. 10
1.1. Electrical Characteristics .............................................................................................. 10
1.2. Thermal Conditions ...................................................................................................... 21
1.3. Absolute Maximum Ratings..........................................................................................21
2. System Overview ...............................................................................................................22
2.1. Power ........................................................................................................................... 24
2.1.1. Voltage Supply Monitor (VMON0) ....................................................................... 24
2.1.2. Device Power Modes........................................................................................... 24
2.1.3. Suspend Mode..................................................................................................... 25
2.1.4. Sleep Mode.......................................................................................................... 25
2.1.5. Low Power Active Mode ...................................................................................... 26
2.1.6. Low Power Idle Mode ..........................................................................................26
2.2. I/O................................................................................................................................. 26
2.2.1. General Features.................................................................................................26
2.2.2. Crossbar .............................................................................................................. 26
2.3. Clocking........................................................................................................................ 27
2.4. Counters/Timers and PWM ..........................................................................................27
2.4.1. Programmable Counter Array (PCA0) ................................................................. 27
2.4.2. Timers (Timer 0, Timer 1, Timer 2, and Timer 3)................................................. 27
2.5. Communications and other Digital Peripherals ............................................................ 28
2.5.1. Universal Asynchronous Receiver/Transmitter (UART0) .................................... 28
2.5.2. Serial Peripheral Interface (SPI0) ........................................................................ 28
2.5.3. System Management Bus / I2C (SMBus0) .......................................................... 28
2.5.4. High-Speed I2C Slave (I2CSLAVE0)................................................................... 29
2.5.5. 16/32-bit CRC (CRC0)......................................................................................... 29
2.6. Analog Peripherals ....................................................................................................... 29
2.6.1. 10-Bit Analog-to-Digital Converter (ADC0) .......................................................... 29
2.7. Digital Peripherals ........................................................................................................30
2.7.1. Direct Memory Access (DMA0) ........................................................................... 30
2.7.2. Multiply and Accumulate (MAC0) ........................................................................ 30
2.8. Reset Sources..............................................................................................................30
2.9. Unique Identifier ........................................................................................................... 30
2.10.On-Chip Debugging ..................................................................................................... 30
3. Pin Definitions.................................................................................................................... 31
3.1. C8051F970/3 QFN-48 Pin Definitions.......................................................................... 31
3.2. C8051F971/4 QFN-32 Pin Definitions.......................................................................... 35
3.3. C8051F972/5 QFN-24 Pin Definitions.......................................................................... 38
4. Ordering Information .........................................................................................................41
5. QFN-48 Package Specifications ...................................................................................... 43
5.1. QFN-48 Package Marking............................................................................................ 45
6. QFN-32 Package Specifications ....................................................................................... 46
6.1. QFN-32 Package Marking............................................................................................ 49
7. QFN-24 Package Specifications ....................................................................................... 50
7.1. QFN-24 Package Marking............................................................................................ 53
8. Memory Organization ........................................................................................................54
8.1. Program Memory.......................................................................................................... 55
Rev 1.1
2





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