dsPIC33EP512MU814 Signal Controllers Datasheet

dsPIC33EP512MU814 Datasheet, PDF, Equivalent


Part Number

dsPIC33EP512MU814

Description

16-bit Microcontrollers and Digital Signal Controllers

Manufacture

Microchip

Total Page 30 Pages
Datasheet
Download dsPIC33EP512MU814 Datasheet


dsPIC33EP512MU814
dsPIC33EPXXX(GP/MC/MU)806/810/814
and PIC24EPXXX(GP/GU)810/814
16-Bit Microcontrollers and Digital Signal Controllers with
High-Speed PWM, USB and Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS
3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS
Core: 16-Bit dsPIC33E/PIC24E CPU
• Code-Efficient (C and Assembly) architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL Plus Hardware Divide
• 32-Bit Multiply Support
Clock Management
• 2% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 1.0 mA/MHz Dynamic Current (typical)
• 60 µA IPD Current (typical)
High-Speed PWM
• Up to Seven PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 8.32 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• Two Independent ADC modules:
- One ADC configurable as 10-bit, 1.1 Msps with four
S&H or 12-bit, 500 ksps with one S&H
- One 10-bit ADC, 1.1 Msps with four S&H
- Eight S&H using both ADC 10-bit modules
- 24 analog channels (64-pin devices) up to 32 analog
channels (100/121/144-pin devices)
• Flexible and Independent ADC Trigger Sources
• Comparators:
- Up to three Analog Comparator modules
- Programmable references with 32 voltage points
Timers/Output Compare/Input Capture
• 27 General Purpose Timers:
- Nine 16-bit and up to four 32-bit Timers/Counters
- 16 OC modules configurable as Timers/Counters
- Two 32-bit Quadrature Encoder Interface (QEI)
modules configurable as Timers/Counters
• 16 IC modules
• Peripheral Pin Select (PPS) to allow Function Remap
• Real-Time Clock and Calendar (RTCC) module
Communication Interfaces
• USB 2.0 OTG-Compliant Full-Speed Interface
• Four UART modules (15 Mbps)
- Supports LIN/J2602 protocols and IrDA®
• Four 4-Wire SPI modules (15 Mbps)
• Two ECAN™ modules (1 Mbaud) CAN 2.0B Support
• Two I2C modules (up to 1 Mbaud) with SMBus Support
• Data Converter Interface (DCI) module with Support for
I2S and Audio Codecs
• PPS to allow Function Remap
• Parallel Master Port (PMP)
• Programmable Cyclic Redundancy Check (CRC)
Direct Memory Access (DMA)
• 15-Channel DMA with User-Selectable
Priority Arbitration
• UART, USB, SPI, ADC, ECAN™, IC, OC, Timers,
DCI/I2S, PMP
Input/Output
• Sink/Source 10 mA on All Pins
• 5V Tolerant Pins
• Selectable Open-Drain, Pull-ups and Pull-Downs
• Up to 5 mA Overvoltage Clamp Current
• External Interrupts on All I/O pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) Planned
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC) Planned
• Class B Safety Library, IEC 60730
Debugger Development Support
• In-Circuit and In-Application Programming
• Five Program and Three Complex Data Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
2009-2012 Microchip Technology Inc.
DS70616G-page 1

dsPIC33EP512MU814
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
dsPIC33EPXXX(GP/MC/MU)806/810/814
and PIC24EPXXX(GP/GU)810/814
PRODUCT FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in
Table 1. Their pinout diagrams appear on the following
pages.
TABLE 1:
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
CONTROLLER FAMILIES
Remappable Peripherals
Device
dsPIC33EP256MU806 64
QFN,
TQFP
280 28 9 16 16
8
2
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
24 ch
1
Y 51
100 TQFP
dsPIC33EP256MU810
280 28 9 16 16
121 TFBGA
12
2
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 83
dsPIC33EP256MU814
144
TQFP,
LQFP
280
28
9
16
16
14
2
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 122
dsPIC33EP512GP806 64
QFN,
TQFP
536 52 9 16 16
— —4
4
2
5 15 1
3/4
1
2
1
2 ADC,
24 ch
Y
53
dsPIC33EP512MC806 64
QFN,
TQFP
536 52 9 16 16
8
2
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
24 ch
Y
53
100 TQFP
dsPIC33EP512MU810
536 52 9 16 16
121 TFBGA
12
2
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 83
dsPIC33EP512MU814
144
TQFP,
LQFP
536
52
9
16
16
14
2
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 122
PIC24EP256GU810
100 TQFP
280 28 9 16 16
121 TFBGA
0
0
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 83
PIC24EP256GU814
144
TQFP,
LQFP
280
28
9
16
16
0
0
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 122
PIC24EP512GP806
64
QFN,
TQFP
586 52 9 16 16
— —4
4
2
5 15 1
3/4
1
2
1
2 ADC,
24 ch
Y
53
PIC24EP512GU810
100 TQFP
536 52 9 16 16
121 TFBGA
0
0
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 83
PIC24EP512GU814
144
TQFP,L
QFP
536
52
9
16
16
0
0
4
4
2
5 15 1
3/4
1
2
1
2 ADC,
32 ch
1
Y 122
Note 1:
2:
3:
4:
5:
6:
7:
8:
Flash size is inclusive of 24 Kbytes of auxiliary Flash. Auxiliary Flash supports simultaneous code execution and self-erase/programming.
Refer to Section 5. “Flash Programming” (DS70609) in the “dsPIC33E/PIC24E Family Reference Manual”.
RAM size is inclusive of 4 Kbytes of DMA RAM (DPSRAM) for all devices.
Up to eight of these timers can be combined into four 32-bit timers.
Eight out of nine timers are remappable.
PWM Faults and Sync signals are remappable.
Four out of five interrupts are remappable.
Comparator output is remappable.
The ADC2 module supports 10-bit mode only.
DS70616G-page 2
2009-2012 Microchip Technology Inc.


Features dsPIC33EPXXX(GP/MC/MU)806/810/814 and PI C24EPXXX(GP/GU)810/814 16-Bit Microcont rollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced A nalog Operating Conditions • 3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS • 3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS Core: 16-Bit dsPIC33E/PIC24 E CPU • Code-Efficient (C and Assembl y) architecture • Two 40-Bit Wide Acc umulators • Single-Cycle (MAC/MPY) wi th Dual Data Fetch • Single-Cycle Mix ed-Sign MUL Plus Hardware Divide • 32 -Bit Multiply Support Clock Management • 2% Internal Oscillator • Programm able PLLs and Oscillator Clock Sources • Fail-Safe Clock Monitor (FSCM) • Independent Watchdog Timer • Fast Wak e-up and Start-up Power Management • Low-Power Management modes (Sleep, Idle , Doze) • Integrated Power-on Reset a nd Brown-out Reset • 1.0 mA/MHz Dynam ic Current (typical) • 60 µA IPD Cur rent (typical) High-Speed PWM • Up to Seven PWM Pairs with Independent Timing • Dead Time for Rising and Falling Edges • 8.32 ns PWM Resolu.
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