D720133 UPD720133 Datasheet

D720133 Datasheet, PDF, Equivalent


Part Number

D720133

Description

UPD720133

Manufacture

NEC

Total Page 30 Pages
Datasheet
Download D720133 Datasheet


D720133
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720133
USB2.0 to IDE Bridge
The µPD720133 is designed to function as a bridge between USB 2.0 and ATA/ATAPI. The µPD720133 complies
with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The
µPD720133 consists of a CISC processor, an ATA/ATAPI controller, an endpoint controller (EPC), a serial interface
engine (SIE), and an USB2.0 transceiver. The USB2.0 protocol and class specific protocols (bulk only protocol) are
handled by the USB2.0 transceiver, the SIE and the EPC. The V30MZ CISC processor in the µPD720133 takes care of
the activities in the transport layer. The firmware controlling the µPD720133 is located in an embedded ROM.
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
• Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
• USB2.0 high-speed bus powered device capability
• Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID: 40001985)
• One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
• USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
• Automatic chirp assertion and full-/high-speed mode change
• USB Reset, Suspend and Resume signaling detection
• Supports power control functionality for IDE device as CD-ROM and HDD
• Supports set feature (TEST_MODE) functionality
• System Clock is generated by 30 MHz X’tal
• 2.5 V and 3.3 V power supply
ORDERING INFORMATION
Part Number
µPD720133GB-YEU-A
µPD720133GB-YEU-Y
Package
64-pin plastic TQFP (fine pitch) (10 × 10) Lead-free product
64-pin plastic TQFP (fine pitch) (10 × 10) High heat-resistance product
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17100EJ2V0DS00 (2nd edition)
Date Published June 2004 NS CP (N)
Printed in Japan
The mark shows major revised points.
2004

D720133
BLOCK DIAGRAM
CPU Core
(V30MZ)
RAM
2 Kbytes x 2
ROM
12 Kbytes
Bus Bridge
DMAC
INTC
µPD720133
EPC2_V2
DCC
IDEC_V2
Timer
PIO
GPIO
PHY_V2
USB Bus
IDE Bus
GPIO
Direct Bus
Direct Command Bus
Serial
ROM
V30MZ
RAM
ROM
PHY_V2
EPC2_V2
IDEC_V2
DCC
Bus Bridge
INTC
GPIO
PIO
: CISC CPU core
: 4-Kbyte work RAM for firmware
: 12-Kbyte ROM for built-in firmware
: USB2.0 transceiver with serial interface engine
: Endpoint controller
: IDE controller
: ATA direct command controller
: Internal / external bus controller and DMA controller
: Interrupt controller (82C59 like)
: General purpose 3-bit I/O controller
: Multipurpose 2-bit I/O controller
2 Preliminary Data Sheet S17100EJ2V0DS


Features PRELIMINARY DATA SHEET MOS INTEGRATED C IRCUIT µPD720133 USB2.0 to IDE Bridge The µPD720133 is designed to functio n as a bridge between USB 2.0 and ATA/A TAPI. The µPD720133 complies with the Universal Serial Bus Specification Revi sion 2.0 full-/high-speed signaling and works up to 480 Mbps. The µPD720133 consists of a CISC processor, an ATA/AT API controller, an endpoint controller (EPC), a serial interface engine (SIE), and an USB2.0 transceiver. The USB2.0 protocol and class specific protocols ( bulk only protocol) are handled by the USB2.0 transceiver, the SIE and the EPC . The V30MZ CISC processor in the µPD7 20133 takes care of the activities in t he transport layer. The firmware contro lling the µPD720133 is located in an e mbedded ROM. FEATURES • Compliant wi th Universal Serial Bus Specification R evision 2.0 (Data Rate 12/480 Mbps) • Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ult ra DMA Mode 0-4) • USB2.0 high-speed bus powered device capability • Cert.
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