1-Bit DRAM. MK4564E-20 Datasheet
65,536 x 1-BIT DYNAMIC RAM
o Recognized industry standard 16-pin configuration from
o Single +5V (± 10%) supply operation
o On chip substrate bias generator for optimum
o Low power: 300 mW active, max
22 mW standby, max
o 150 ns access time, 260 ns cycle time (MK4564-15)
200 ns access time, 330 ns cycle time (MK4564-20)
o Extended DOUT hold using CAS control (Hidden Refresh)
o Common I/O capability using "early write"
o Read, Write, Read-Write, Read-Modify-Write and Page-
o All inputs TTL compatible, low capacitance, and
protected against static charge
o Scaled POLY 5™ technology
o 128 refresh cycles (2 msec)
Pin 9 is not needed for refresh
The MK4564 is the new generation dynamic RAM.
Organized 65,536 words by 1 bit, it is the successor to the
industry standard MK4116. The MK4564 utilizes Mostek's
Scaled POLY 5 process technology as well as advanced
circuit techniques to provide wide operating margins, both
internally and to the system user. The use of dynamic
circuitry throughout, including the 512 sense amplifiers,
assures that power dissipation is minimized without any
sacrifice in speed or internal and external operating
margins. Refresh characteristics have been chosen to
maximize yield (low cost to user) while maintaining
compatibility between dynamic RAM generations.
Multiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permit the MK4564 to
be packaged in a standard 16-pin DIP with only 15 pins
required for basic functionality. The MK4564 is designed to
be compatible with the JEDEC standards for the 64K x 1
The output ofthe MK4564 can be held valid up to 10 ~sec by
holding CAS active low. This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.
The 64K RAM from Mostek is the culmination of several
years of circuit and process development, proven in
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Available soon in MIL-STD-883 Class B (MKB).
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee supply relative to V55 .....•......................•................•....•.•..... -1.0 V to +7.0 V
Operating Temperature, TA (Ambient) ..........................•.•................................ O°C to +70C
Storage Temperature (Ceramic) .....•................................•....................... -65°C to +150°C
Storage Temperature (Plastic) ................•..................................•....•.•.... -55°C to +125°C
Power Dissipation .•..•.......................................•.....................•............... 1 Watt
Short Circuit Output Current .......•.................•...............................................50 mA
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(O°C :$ TA :$ 70°C)
Input High (Logic 1) Voltage,
Input Low (Logie 0)
Voltage, All Inputs
V ee +1
DC ELECTRICAL CHARACTERISTICS
=(O°C:$ TA :$ 70°C) (Vee 5.0 V ± 10%)
lec1 OPERATING CURRENT
Average power supply operating current
=(RAS, CAS cycling; tRe 330 ns)
ICC2 STANDBY CURRENT
=Power supply standby current (RAS V1H,
=DOUT High Impedance)
ICC3 RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
= =(RAS cycling, CAS V1H; tRC tRC min.)
ICC4 PAGE MODE CURRENT
Average power supply current, page mode
= =operation' (RA'S V1L, tRA5 tRA5 max., CAS
=cycling; tpc tpc min.)
II(L) INPUT LEAKAGE
Input leakage current, any input
(0 V :$ V1N :$ Vcd, all other pins not under
test =0 V
IO(L) OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
OV:$ VOUT :$ Vcd
=VOH Output High (Logic 1) voltage (lOUT -5 mAl
=VOL Output Low (Logic 0) voltage (lOUT 4.2 mAl
-10 10 iJ-A
-10 10 iJ-A
1. All voltages referenced to VSS.
2. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pause of 500 jJ.S is required after power-up followed by any 8 i l l
cycles before proper device operation is achieved. Note that RAS may be
cycled during the initial pause.
4. AC characteristics assume tT = 5 ns.
5. VIH min. and VIL max. are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL.
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C ~ TA ~ 70°C) is
7. Load = 2 TIL loads and 50 pF.
8. Assumes that tRCD ~ tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
9. Assumes that tRCD 2': tRCD (max).
10. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
11. Operation within the tRCD (max) limit insures that tRAC (max) can be met.
tRCD (max) is specified as a reference point only; if tRCD is greater than the
~~~~~ied tRCD (max) limit. then access time is controlled exclusively by
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. These ~eters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write cycles.
14. twcs, tCWD, and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs 2': twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle.lftcWD 2':tCWD (min) and tRWD 2':
tRWD (min)the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAS goes back to VIH) is
15. In addition to meeting the transition rate specification, all input signals must
transmit between VIH and VIL (or between VIL and VIH) in a monotonic
16. Effective capacitance calculated from the equation C =I b.twith b. V =3 volts
and power supply at nominal level.
17. CAS = VIH to disable DOUT.
18. Includes the DC level and all instantaneous Signal excursions.
19. WRITE = don't care. Data out d~nds on the state of CAS. If CAS = VIH, data
output is high impedance. If CAS =VIL, the data output will contain data
from the last valid read cycle.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
=(3,4,5,15) (O°C :::; TA:::; 70°C), Vcc 5.0 V ± 10%
tRELREL t RC
Random read or write cycle time
tRELREL tRMw Read modify write cycle time
Page mode cycle time
tRELQV t RAC
tREHREL t RP
tRELREH t RAS
tCELREH t RSH
tRELCEL t RCD
Access ti me from RAS
Access ti me from CAS
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
Read command hold time
referenced to RAS
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address hold time
referenced to RAS
150 10,000 200 10,000
85 10,000 115 10,000
20 65 25 85