1-Bit DRAM. MK4564N-12 Datasheet
65,536 x 1-BIT DYN(AMIC RAM
o Recognized industry standard 16-pin configuration
o Single +6 V (± 1()oAI) supply operation
o On chip substrate bias generator for optimum
o Low power: 330 mW active, max
22 mW standby, max
o 120 ns access time, 220 ns cycle time
o Extended Dour hold using CAS control (Hidden Refresh)
o Common 1/0 capability using "early write"
o Read, Write, Read-Write, Read-Modify-Write and Page-
o All inputs TIL compatible, low capacitance, and
protected against static charge
o Scaled POLY 6™ technology
o 128 refresh cycles (2 msec)
Pin 9 is not needed for refresh
The MK4664 is the new generation dynamic RAM.
Organized 66,636 words by 1 bit, it is the successor to the
industry standard MK4116. The MK4664 utilizes Mostek's
Scaled Poly 6 process technology as well as advanced
circuit techniques to provide wide operating margins, both
internally and to the system user. The use of dynamic
circuitry throughout, including the 612 sense amplifiers,
assures that power dissipation is minimized without any
sacrifice in speed or internal and external operating
margins. Refresh characteristics have been chosen to
maximize yield (low cost to user) while maintaining
compatibility between dynamic RAM generations.
Multiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permits the MK4664 to
be packaged in a standard 16-pin DIP with only 16 pins
required for basic functionality. The MK4664 is designed to
be compatible with the JEDEC standards for the 64K x 1
The output ofthe MK4664 can be held valid up to 10 J.Lsec by
holding CAS active low. This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.
The 64K RAM from Mostek is the culmination of several
years of circuit and process development, proven in
DUAL-IN-LiNE PACKAGE LEADLESS CHIP CARRIER
D'N (D) 2
14 DOUT (0)
WfiiTE(WI 3 I
Available soon in MIL-STD-883 Class B (MKB).
ABSOLUTE MAXIMUM RATINGS·
Voltage on Vcc supply relative to Vss .•.....••..........•.......•..•..........••....•......•••• -1.0 V to +7.0 V
Operating Temperature, TA (Ambient) ...••..••...................•...•...........................•O°C to +70C
Storage Temperature (Ceramic) ....••..•.............•..•..............................•..... -65°C to +150°C
Storage Temperature (Plastic) ...•.•.•..............•...•.........•.....••.......•.......••.. -55°C to +125°C
Power Dissipation .....•...•....•..•...•..........•..••.........•.....••........................•... 1 Watt
Short Circuit Output Current ...•.•.......•.•..•..•....•.......•..•..•....••.•..............••.•..•.•.50 mA
·Stresses greater than those listed undar "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those Indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(O°C S TA ::5 70°C)
Input High (Logic 1) Voltage,
Input Low (Logic 0)
Voltage, All Inputs
4.5 5.0 5.5
2.4 - Vcc+1 V
.8 V 1,18
DC ELECTRICAL CHARACTERISTICS
(O°C S TA ::5 70°C) (Vcc = 5.0 V ± 10%)
Average power supply operating current
(RAS, CAS cycling; tRC =tRC min.)
Power supply standby current
DOUT =High Impedance)
R'AS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS =V1H; tpc =tpc min.)
PAGE MODE CURRENT
Average power supply current, page mode
coypcelirnagti;ontpc(R=AStpc=mVi1nL,.)tRAS =tRAS max., CAS
Input leakage current, any input
Output leakage current
OV SVOUT :5Vcd
Output High (Logic 1) voltage (lOUT =-5 mA)
Output Low (Logic 0) voltage (lOUT =4.2 mA)
-10 10 JJ.A
-10 10 JJ.A
1. All voltages referenced to VSS.
2. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pause of 500 /-Is is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. Note that RAS may be
cycled during the initial pause.
4. AC characteristics assume If =5 ns.
5. VIH min. and VIL max. are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL'
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C S TA S 70°C) is
7. Load = 2 TIL loads and 50 pF.
8. Assumes that tRCo-S tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
9. Assumes that tRCD ;::: tRCD (max).
10. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
11. Operation within the tRCD (max) limit permits tRAC (max) to be met. tRCD
(max) is specified as a reference point only; if tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. These parameters are referenced to CAS leading edge in early write cycles
and to WRiTE leading edge in delayed write or read-modify-write cycles.
14. twcs, tCWD, and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs ;::: twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle.lftCWD ;:::tCWD(min)andtRWD;:::
tRWD (min) the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAS goes back to VIH) is
15. In addition to meeting the transition rate specification, all input signals must
transmit between VIH and VIL (or between VIL and VIH) in a monotonic
16. Effective capacitance calculated from theequation C = I Atwith A V = 3 volts
and power supply at nominal level.
17. CAS = VIH to disable DOUT.
18. Includes the DC level and all instantaneous signal excursions.
19. WRITE = don't care. Data out depends on the state of CAS. If CAS = VIH, data
output is high impedance. If CAS = VIL, the data output will contain data
from the last valid read cycle.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
=(3,4,5,15) (O°C :'5 TA:5 70°C), Vcc 5.0 V ± 10%
Random read or write cycle time
Read-modify-write cycle time
Page mode cycle time
Access time from RAS
Access time from CAS
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
Read command hold time referenced to RAS
Row address set-up time
Row address hold ti me
Column address set-up time
Column address hold time
Column address hold time referenced to RAS