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PL613-21

Part Number	PL613-21
Manufacturer	Micrel
Description	Programmable 3-PLL Clock
Published	Feb 17, 2015
Detailed Description	PL613-21 Ultra Low Power PicoPLL, Programmable 3-PLL Clock IC FE AT UR E S  Designed for PCB Space Savings with 3 LowP...
Datasheet	PL613-21 PDF File

Overview

PL613-21 Ultra Low Power PicoPLL, Programmable 3-PLL Clock IC FE AT UR E S  Designed for PCB Space Savings with 3 LowPower Programmable PLLs  Ultra Low-Power Consumption  Ultra-Low Power Down Mode, <5A Typical  CLK1 Capable of Generating 32.
768kHz  Individual Output Buffer VDD Pins for Flexible Output Voltages, 1.
8V to 3.
3V, ±10%  Individual PLL Power Down Control  Output Frequency (based on VDD_CORE voltage): o <65MHz @ 1.
8V operation o <90MHz @ 2.
5V operation o <125MHz @ 3.
3V operation  Input Frequency: o Fundamental Crystal: 10MHz to 40MHz o Reference Input: 10MHz to 200MHz  Active Low or Hi-Z Disabled Output State  1.
8V to 3.
3V, ±10% Core Power Supply  1.
8V to 3.
3V, ±10% Buffer Power Supply  Operating Temperature Ranges: o Commercial: 0C to 70C o Industrial: -40C to 85C  Available in GREEN/RoHS Compliant 3x3 QFN Package PIN CONFIGURATION GND XIN/FIN XOUT VDD_CORE PDB4 CLK4 VDD4 PDB1 12 11 10 9 13 8 14 P61321 7 XXX(I) 15 LLL 6 16 5 1 23 4 CLK3 PDB2_3 VDD2_3 CLK2 CLK1 VDD1 GND GND QFN-16L Package DESCRIPTION The PL613-21 is an advanced three PLL design based on PicoPLL, the world’s smallest programmable clock technology.
This advanced technology allows the PL613 -21 to fit in to a small 3x3mm QFN package for high performance, low-power, small form-factor applications.
By using the individual output buffer VDD pins, the PL613-21 can support multiple output voltage requirements.
In addition, CLK1 has the ability to generate kHz outputs and is ideal for generating 32.
768kHz outputs.
The unique power down features of the PL613-21 allows the user to shut down individual PLLs when the corresponding clock output is disabled using the PDB pins.
The output drive strength can be individually programmed on each output to Low (4mA), Standard (8mA) or High (16mA) drive.
In addition, the disabled state of the clock outputs can be programmed as Hi-Z or Active Low.
Besides its small form factor and multiple outputs that can reduce overall system cos...

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