PH3030AL level FET Datasheet

PH3030AL Datasheet, PDF, Equivalent


Part Number

PH3030AL

Description

N-channel TrenchMOS logic level FET

Manufacture

NXP

Total Page 14 Pages
Datasheet
Download PH3030AL Datasheet


PH3030AL
PH3030AL
N-channel TrenchMOS logic level FET
Rev. 03 — 12 January 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing and consumer applications.
1.2 Features and benefits
„ High efficiency due to low switching
and conduction losses
„ Suitable for logic level gate drive
sources
1.3 Applications
„ Consumer applications
„ Desktop Voltage Regulator Module
(VRM)
„ Notebook Voltage Regulator Module
(VRM)
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS drain-source voltage Tj 25 °C; Tj 175 °C
- - 30 V
ID drain current
Tmb = 25 °C; VGS = 10 V;
[1] -
-
100 A
see Figure 1
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
- - 81 W
Dynamic characteristics
QGD
gate-drain charge
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
and 15
- 5.1 - nC
QG(tot) total gate charge
Static characteristics
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
- 21 - nC
RDSon
drain-source
VGS = 10 V; ID = 15 A;
on-state resistance Tj = 25 °C
-
2.19 3
m
[1] Continuous current is limited by package.

PH3030AL
NXP Semiconductors
PH3030AL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin Symbol Description
1S
source
2S
source
3S
source
4G
gate
mb D
mounting base; connected to
drain
3. Ordering information
Simplified outline
mb
1234
SOT669 (LFPAK)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
PH3030AL
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
4. Limiting values
Version
SOT669
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
VDGR
VGS
ID
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Source-drain diode
Conditions
Tj 25 °C; Tj 175 °C
Tj 25 °C; Tj 175 °C; RGS = 20 k
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1
tp 10 µs; pulsed; Tmb = 25 °C; see Figure 3
Tmb = 25 °C; see Figure 2
[1]
[1]
IS source current
ISM peak source current
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source avalanche
energy
Tmb = 25 °C;
tp 10 µs; pulsed; Tmb = 25 °C
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup 30 V;
RGS = 50 ; unclamped
[1]
[1] Continuous current is limited by package.
Min Max Unit
- 30 V
- 30 V
-20 20
V
- 96 A
- 100 A
- 496 A
- 81 W
-55 175 °C
-55 175 °C
- 100 A
- 496 A
- 75 mJ
PH3030AL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 12 January 2010
© NXP B.V. 2010. All rights reserved.
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Features PH3030AL N-channel TrenchMOS logic level FET Rev. 03 — 12 January 2010 Produ ct data sheet 1. Product profile 1.1 General description Logic level N-chann el enhancement mode Field-Effect Transi stor (FET) in a plastic package using T renchMOS technology. This product is de signed and qualified for use in computi ng and consumer applications. 1.2 Feat ures and benefits „ High efficiency du e to low switching and conduction losse s „ Suitable for logic level gate dri ve sources 1.3 Applications „ Consume r applications „ Desktop Voltage Regul ator Module (VRM) „ Notebook Voltage Regulator Module (VRM) 1.4 Quick refer ence data Table 1. Quick reference Sy mbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 30 V ID dr ain current Tmb = 25 °C; VGS = 10 V; [1] - - 100 A see Figure 1 Ptot to tal power dissipation Tmb = 25 °C; se e Figure 2 - - 81 W Dynamic character istics QGD gate-drain charge VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure.
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