D-S MOSFET. B3965D Datasheet


B3965D MOSFET. Datasheet pdf. Equivalent


B3965D


N- and P-Channel 40-V (D-S) MOSFET
B3965D
N- and P-Channel 40-V (D-S) MOSFET

General Description
The B3965D is the N- and P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits with high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
Pin Configuration

Features
40V/5.2A, RDS(ON)=40mΩ@VGS=10V (N-Ch) 40V/4.9A, RDS(ON)=45mΩ@VGS=4.5V (N-Ch) -40V/-4.5A, RDS(ON)=54mΩ@VGS=-10V (P-Ch) -40V/-3.9A, RDS(ON)=72mΩ@VGS=-4.5V (P-Ch) Super High Density Cell Design For Extremely Low RDS(ON) Exceptional On-Resistance and Maximum DC Current Capability TO-252 Package
Applications
Power Management in Note book Portable Equipment Battery Powered System DC/DC Converter Load Switch LCD Display inverter

℃Absolute Maximum Ratings (TA=25 Unless Otherwise Noted):

Parameter

Drain-Source Voltage

Gate-Source Voltage
℃Continuous Drain
Current(tJ=150 )

℃TA=25 ℃TA=70

Pulsed Drain Current

Continuous Source Current (Diode Conduction)

Avalanche Energy with Single Pulse(L=0.1mH)

℃TA=25

Maximum Power Dissipation

℃TA=70

Operating Junction Temperature

Thermal Resistance-Junct...



B3965D
B3965D
N- and P-Channel 40-V (D-S) MOSFET
General Description
The B3965D is the N- and P-Channel logic
enhancement mode power field effect transistors
are produced using high cell density, DMOS trench
technology. This high density process is especially
tailored to minimize on-state resistance. These
devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery
powered circuits with high-side switching, and low
in-line power loss are needed in a very small outline
surface mount package.
Pin Configuration
Features
40V/5.2A, RDS(ON)=40m@VGS=10V (N-Ch)
40V/4.9A, RDS(ON)=45m@VGS=4.5V
(N-Ch)
-40V/-4.5A, RDS(ON)=54m@VGS=-10V
(P-Ch)
-40V/-3.9A, RDS(ON)=72m@VGS=-4.5V
(P-Ch)
Super High Density Cell Design For
Extremely Low RDS(ON)
Exceptional On-Resistance and
Maximum DC Current Capability
TO-252 Package
Applications
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
LCD Display inverter
Absolute Maximum Ratings (TA=25 Unless Otherwise Noted):
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current(tJ=150 )
TA=25
TA=70
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Avalanche Energy with Single Pulse(L=0.1mH)
TA=25
Maximum Power Dissipation
TA=70
Operating Junction Temperature
Thermal Resistance-Junction to Ambient*
Thermal Resistance-Junction to Case
Symbol
VDSS
VGSS
ID
IDM
IS
EAS
PD
TJ
RθJA
RθJC
N-Channel
P-Channel
30 -30
±20 ±20
6.9 -6.1
5.5 -4.9
30 -30
1.7 -1.7
10 20
2.0
1.3
-55 to 150
Steady 75 Steady 65
10sec 47 10sec 35
44 30
Unit
V
V
A
A
A
mJ
W
/W
/W
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