EFFECT TRANSISTOR. NP109N04PUK Datasheet

NP109N04PUK TRANSISTOR. Datasheet pdf. Equivalent

Part NP109N04PUK
Description MOS FIELD EFFECT TRANSISTOR
Feature NP109N04PUK MOS FIELD EFFECT TRANSISTOR Preliminary Data Sheet R07DS0544EJ0100 Rev.1.00 Sep 23, 201.
Manufacture Renesas
Datasheet
Download NP109N04PUK Datasheet



NP109N04PUK
NP109N04PUK
MOS FIELD EFFECT TRANSISTOR
Preliminary Data Sheet
R07DS0544EJ0100
Rev.1.00
Sep 23, 2011
Description
The NP109N04PUK is N-channel MOS Field Effect Transistor designed for high current switching applications.
Features
Super low on-state resistance
RDS(on) = 1.75 mΩ MAX. (VGS = 10 V, ID = 55 A)
Low Ciss: Ciss = 7200 pF TYP. (VDS = 25 V)
Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
NP109N04PUK-E1-AY 1
NP109N04PUK-E2-AY 1
Lead Plating
Pure Sn (Tin)
Tape 800p/reel
Packing
Taping (E1 type)
Taping (E2 type)
Note: 1. Pb-free (This product does not contain Pb in the external electrode.)
Package
TO-263 (MP-25ZP)
Absolute Maximum Ratings (TA = 25°C)
Item
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) 1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
Storage Temperature
Repetitive Avalanche Current 2
Repetitive Avalanche Energy 2
Symbol
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
PT2
Tch
Tstg
IAR
EAR
Ratings
40
±20
±110
±440
250
1.8
175
55 to +175
56
313
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
0.60
83.3
°C/W
°C/W
Notes: 1. TC = 25°C, PW 10 μs, Duty Cycle 1%
2. RG = 25 Ω, VGS = 20 Æ 0 V
R07DS0544EJ0100 Rev.1.00
Sep 23, 2011
Page 1 of 6



NP109N04PUK
NP109N04PUK
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance 1
Drain to Source On-state
Resistance 1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage 1
Reverse Recovery Time
Reverse Recovery Charge
Note: 1. Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
2.0
50
TYP.
3.0
100
1.40
7200
1040
390
30
16
105
13
126
32
31
0.9
62
110
MAX.
1
±100
4.0
1.75
10800
1560
710
70
40
210
40
189
1.5
Chapter Title
Unit
μA
nA
V
S
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μ A
VDS = 5 V, ID = 55 A
VGS = 10 V, ID = 55 A
VDS = 25 V,
VGS = 0 V,
f = 1 MHz
VDD = 20 V, ID = 55 A,
VGS = 10 V,
RG = 0 Ω
VDD = 32 V,
VGS = 10 V,
ID = 110 A
IF = 110 A, VGS = 0 V
IF = 110 A, VGS = 0 V,
di/dt = 100 A/μ s
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
ID
VDD
IAS
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG. RG
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
90%
VGS
90%
10% 10%
tr td(off)
tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
R07DS0544EJ0100 Rev.1.00
Sep 23, 2011
Page 2 of 6





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