EFFECT TRANSISTOR. NP90N055VUK Datasheet

NP90N055VUK TRANSISTOR. Datasheet pdf. Equivalent

Part NP90N055VUK
Description MOS FIELD EFFECT TRANSISTOR
Feature Preliminary Data Sheet NP90N055VUK MOS FIELD EFFECT TRANSISTOR R07DS0578EJ0100 Rev.1.00 Nov 29, 20.
Manufacture Renesas
Datasheet
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Preliminary Data Sheet NP90N055VUK MOS FIELD EFFECT TRANSIS NP90N055VUK Datasheet
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NP90N055VUK
Preliminary Data Sheet
NP90N055VUK
MOS FIELD EFFECT TRANSISTOR
R07DS0578EJ0100
Rev.1.00
Nov 29, 2011
Description
The NP90N055VUK is N-channel MOS Field Effect Transistor designed for high current switching applications.
Features
Super low on-state resistance
RDS(on) = 3.85 mMAX. (VGS = 10 V, ID = 45 A)
Low Ciss: Ciss = 4000 pF TYP. (VDS = 25 V)
Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
NP90N055VUK-E1-AY *1
NP90N055VUK-E2-AY *1
Lead Plating
Pure Sn (Tin)
Packing
Tape 2500 p/reel
Taping (E1 type)
Taping (E2 type)
Note: *1 Pb-free (This product does not contain Pb in the external electrode)
Package
TO-252 (MP-3ZP)
Absolute Maximum Ratings (TA = 25°C)
Item
Symbol
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) *1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation (TA = 25°C)
PT2
Channel Temperature
Tch
Storage Temperature
Repetitive Avalanche Current *2
Repetitive Avalanche Energy *2
Tstg
IAR
EAR
Notes: *1 TC = 25°C, PW 10 s, Duty Cycle 1%
*2 RG = 25 , VGS = 20 0 V
Ratings
55
20
90
360
147
1.2
175
–55 to 175
33
108
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
1.02 °C/W
125 °C/W
R07DS0578EJ0100 Rev.1.00
Nov 29, 2011
Page 1 of 6



NP90N055VUK
NP90N055VUK
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance *1
Drain to Source On-state Resistance *1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage *1
Reverse Recovery Time
Reverse Recovery Charge
Note: *1 Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
2.0
30
TYP.
3.0
60
3.20
4000
410
150
25
10
65
6
68
18
18
0.9
47
80
MAX.
1
100
4.0
3.85
6000
620
270
60
30
130
20
102
1.5
Unit
A
nA
V
S
m
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 55 V, VGS = 0 V
VGS = 20 V, VDS = 0 V
VDS = VGS, ID = 250 A
VDS = 5 V, ID = 45 A
VGS = 10 V, ID = 45 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 28 V, ID = 45 A
VGS = 10 V
RG = 0
VDD = 44 V
VGS = 10 V
ID = 90 A
IF = 90 A, VGS = 0 V
IF = 90 A, VGS = 0 V
di/dt = 100 A/s
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG. RG
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VGS
VGS
Wave Form
10%
0
VDD
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off)
tf
ton toff
R07DS0578EJ0100 Rev.1.00
Nov 29, 2011
Page 2 of 6





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