NAND gate. 74HCT00 Datasheet

74HCT00 gate. Datasheet pdf. Equivalent

74HCT00 Datasheet
Recommendation 74HCT00 Datasheet
Part 74HCT00
Description Quad 2-input NAND gate
Feature 74HCT00; 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 7 — 25 November 2015 Product data sheet 1. General des.
Manufacture NXP
Datasheet
Download 74HCT00 Datasheet





NXP 74HCT00
74HC00; 74HCT00
Quad 2-input NAND gate
Rev. 7 — 25 November 2015
Product data sheet
1. General description
The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Input levels:
For 74HC00: CMOS level
For 74HCT00: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74HC00D
40 C to +125 C
74HCT00D
74HC00DB 40 C to +125 C
74HCT00DB
74HC00PW 40 C to +125 C
74HCT00PW
74HC00BQ 40 C to +125 C
74HCT00BQ
Name
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads; body width
3.9 mm
Version
SOT108-1
plastic shrink small outline package; 14 leads; body SOT337-1
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm



NXP 74HCT00
NXP Semiconductors
4. Functional diagram
74HC00; 74HCT00
Quad 2-input NAND gate
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PQD
Fig 1. Logic symbol












PQD
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
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PQD
Fig 3. Logic diagram (one gate)
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Fig 4. Pin configuration SO14 and (T)SSOP14
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7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN14
74HC_HCT00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 15



NXP 74HCT00
NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
6. Functional description
Description
data input
data input
data output
ground (0 V)
supply voltage
Table 3.
Input
nA
L
X
H
Function table[1]
nB
X
L
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Output
nY
H
H
L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14, (T)SSOP14 and
DHVQFN14 packages
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
-
50
65
[2]
-
+7
20
20
25
50
-
+150
V
mA
mA
mA
mA
mA
C
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 15





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