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AT28HC256. 28HC256 Datasheet

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AT28HC256. 28HC256 Datasheet






28HC256 AT28HC256. Datasheet pdf. Equivalent




28HC256 AT28HC256. Datasheet pdf. Equivalent





Part

28HC256

Description

AT28HC256



Feature


Features • Fast Read Access Time – 7 0 ns • Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes – Internal Control Timer • Fast Write Cycle Times – Page Wr ite Cycle Time: 3 ms or 10 ms Maximum 1 to 64-byte Page Write Operation Low Power Dissipation – 80 mA Activ e Current – 3 mA Standby Current • Hardware and Software Data Protection • DA.
Manufacture

ATMEL

Datasheet
Download 28HC256 Datasheet


ATMEL 28HC256

28HC256; TA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 104 or 105 Cycles – Data R etention: 10 Years • Single 5V ± 10% Supply • CMOS and TTL Compatible Inp uts and Outputs • JEDEC Approved Byte -wide Pinout • Full Military and Indu strial Temperature Ranges • Green (Pb /Halide-free) Packaging Option 256K (3 2K x 8) High-speed Parallel EEPROM .


ATMEL 28HC256

AT28HC256 1. Description The AT28HC256 is a high-performance electrically eras able and programmable readonly memory. Its 256K of memory is organized as 32,7 68 words by 8 bits. Manufactured with A tmel’s advanced nonvolatile CMOS tech nology, the AT28HC256 offers access tim es to 70 ns with power dissipation of j ust 440 mW. When the AT28HC256 is desel ected, the standby c.


ATMEL 28HC256

urrent is less than 5 mA. The AT28HC256 is accessed like a Static RAM for the r ead or write cycle without the need for external components. The device contai ns a 64-byte page register to allow wri ting of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally lat ched, freeing the addresses and data bu s for other operat.

Part

28HC256

Description

AT28HC256



Feature


Features • Fast Read Access Time – 7 0 ns • Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes – Internal Control Timer • Fast Write Cycle Times – Page Wr ite Cycle Time: 3 ms or 10 ms Maximum 1 to 64-byte Page Write Operation Low Power Dissipation – 80 mA Activ e Current – 3 mA Standby Current • Hardware and Software Data Protection • DA.
Manufacture

ATMEL

Datasheet
Download 28HC256 Datasheet




 28HC256
Features
Fast Read Access Time – 70 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-byte Page Write Operation
Low Power Dissipation
– 80 mA Active Current
– 3 mA Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Full Military and Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option
256K (32K x 8)
High-speed
Parallel
EEPROM
AT28HC256
1. Description
The AT28HC256 is a high-performance electrically erasable and programmable read-
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers
access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256
is deselected, the standby current is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64
bytes of data are internally latched, freeing the addresses and data bus for other oper-
ations. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected
by DATA Polling of I/O7. Once the end of a write cycle has been detected a new
access for a read or write can begin.
Atmel’s 28HC256 has additional features to ensure high quality and manufacturability.
The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
0007N–PEEPR–9/09




 28HC256
2. Pin Configurations
Pin Name
A0 - A14
CE
OE
WE
I/O0 - I/O7
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
Don’t Connect
2.1 28-lead TSOP Top View
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 CE
26 I/O7
25 I/O6
24 I/O5
23 I/O4
22 I/O3
21 GND
20 I/O2
19 I/O1
18 I/O0
17 A0
16 A1
15 A2
2.2 28-lead PGA Top View
2.3 32-pad LCC, 32-lead PLCC Top View
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
I/O0 13
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
Note: PLCC package pins 1 and 17 are Don’t Connect.
2.4 28-lead Cerdip/Flatpack/SOIC –
Top View
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
2 AT28HC256
0007N–PEEPR–9/09




 28HC256
3. Block Diagram
AT28HC256
4. Device Operation
4.1 Read
The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2 Byte Write
4.3 Page Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of tWC, a read operation will effectively be a polling operation.
The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the
tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition dur-
ing the page write operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.
4.4 DATA Polling
The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime
during the write cycle.
0007N–PEEPR–9/09
3



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