TVS Array. CDNBS08-SLVU2.8-8 Datasheet

CDNBS08-SLVU2.8-8 Array. Datasheet pdf. Equivalent


BOURNS CDNBS08-SLVU2.8-8
Features
RoHS compliant*
Protects up to four I/O ports
Bidirectional configuration
ESD protection
Low capacitance: 6 pF
Applications
Ethernet - 10/100/1000 Base T
Personal digital assistants
Handheld electronics
Cellular phones
Video cards
CDNBS08-SLVU2.8-8 - Low Capacitance TVS Array
General Information
The markets of portable communications, computing and video equipment are challenging
the semiconductor industry to develop increasingly smaller electronic components.
Bourns offers Transient Voltage Suppressor Array combination diodes for surge and ESD
protection applications in an eight lead narrow body SOIC package size format. Bourns®
Chip Diodes conform to JEDEC standards, are easy to handle on standard pick and place
equipment and their flat configuration minimizes roll away.
The Bourns® device will meet IEC 61000-4-2 (ESD), IEC 61000-4-4 (EFT) and IEC
61000-4-5 (Surge) requirements.
Electrical Characteristics (@ TA = 25 °C Unless Otherwise Noted)
Parameter
Symbol
Min.
Peak Pulse Current (tp= 8/20 µs)
Peak Pulse Power (tp= 8/20 µs) 1
Working Voltage
IPP
PPP
VWM
Breakdown Voltage @ 1 mA
Leakage Current @ VWM
Capacitance @ 0 V, 1 MHz
VBR
ID
C
3.0
Snapback Voltage @ 50 mA
2.8
ESD Protection per IEC 61000-4-2
Contact Discharge
Air Discharge
ESD
±8
±15
EFT Protection per IEC 61000-4-4 @ 5/50 ns
EFT
Surge Protection per
IEC 61000-4-5
Clamping Voltage
@ 8/20 µs
@ IP = 5 A 2
@ IP = 24 A 2
@ IPP = 30 A 2
Notes:
1. See Peak Pulse Power vs. Pulse Time.
2. Each differential line pair.
VC
VC
VC
Nom.
6
Thermal Characteristics (@ TA = 25 °C Unless Otherwise Noted)
Parameter
Junction Temperature Range
Storage Temperature Range
Symbol
TJ
TSTG
Min.
-55
-55
Nom.
+25
+25
8765
1234
Max.
30
600
2.8
1.0
60
8.5
15
17
Unit
A
W
V
V
µA
pF
V
kV
A
V
V
V
Max.
+125
+150
Unit
°C
°C
*RoHS Directive 2002/95/EC Jan. 27, 2003 including annex and RoHS Recast 2011/65/EU June 8, 2011.
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.


CDNBS08-SLVU2.8-8 Datasheet
Recommendation CDNBS08-SLVU2.8-8 Datasheet
Part CDNBS08-SLVU2.8-8
Description Low Capacitance TVS Array
Feature CDNBS08-SLVU2.8-8; *RoHS COMPLIANT Features ■ RoHS compliant* ■ Protects up to four I/O ports ■ Bidirectional configura.
Manufacture BOURNS
Datasheet
Download CDNBS08-SLVU2.8-8 Datasheet




BOURNS CDNBS08-SLVU2.8-8
CDNBS08-SLVU2.8-8 - Low Capacitance TVS Array
Product Dimensions
This is an RoHS compliant molded JEDEC narrow body SO-8
package with 100 % Sn plating on the lead frame. It weighs
approximately 15 mg and has a flammability rating of UL 94V-0.
A
Recommended Footprint
A
B
D
7 ° NOM.
3 PLCS.
K
L
45 °
NOM.
B
C
I
J
G
7 ° NOM.
4 PLCS.
4°±4°
H
DIMENSIONS = MILLIMETERS
(INCHES)
E
F
DC
E
Dimensions
A
1.143 - 1.397
(0.045 - 0.065)
B
0.635 - 0.889
(0.025 - 0.035)
C
6.223
(0.245)
MMinin..
D
3.937 - 4.191
(0.155 - 0.165)
E
1.016 - 1.27
(0.040 - 0.050)
Dimensions
A
4.80 - 5.00
(0.189 - 0.197)
B
3.81 - 4.00
(0.150 - 0.157)
C
5.80 - 6.20
(0.228 ± 0.244)
D
0.36 - 0.51
(0.014 - 0.020)
E
1.35 - 1.75
(0.053 - 0.069)
F
0.102 - 0.203
(0.004 - 0.008)
G
0.25 - 0.50
(0.010 - 0.020)
H
0.51 - 1.12
(0.020 - 0.044)
I
0.190 - 0.229
(0.0075 - 0.0090)
J
4.60 - 5.21
(0.181 - 0.205)
K
0.28 - 0.79
(0.011 - 0.031)
L
1.27
(0.050)
Typical Part Marking
CDNBS08-SLVU2.8-8 .....................................................
SL8
How to Order
CD NBS08 - SLVU 2.8 - 8
Common Code
Chip Diode
Package
NBS08 = Narrow Body SOIC8 Package
Model
SLVU = Low Capacitance TVS Array
Working Peak Reverse Voltage
2.8 = 2.8 VRWM (Volts)
Number of Diodes
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.



BOURNS CDNBS08-SLVU2.8-8
CDNBS08-SLVU2.8-8 - Low Capacitance TVS Array
Block Diagram
8765
1234
Device Pinout
Pin
Bidirectional
Common Mode
1 Line 1
2 GND
3 GND
4 Line 4
5 Line 3
6 GND
7 GND
8 Line 2
Bidirectional
Differential
Mode
Line Pair 1
Line Pair 1
Line Pair 2
Line Pair 2
Line Pair 4
Line Pair 4
Line Pair 3
Line Pair 3
Performance Graphs
Peak Pulse Power vs Pulse Time
10,000
1,000
600 W, 8/20 µs Waveform
100
10
0.01
1 10 100
td – Pulse Duration (µs)
1,000
10,000
Pulse Waveform
120
tt
100
80
60
40
20
0
05
Test Waveform Parameters
tt = 8 µs
td = 20 µs
et
|td = t IPP/2
10 15 20 25 30
t – Time (µs)
Power Derating Curve
100
80
Peak Pulse Power
8/20 µs
60
40
20
Average Power
0
0 25 50 75 100 125 150
TL – Lead Temperature (°C)
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)