M29F200BB. 29F200BB Datasheet

29F200BB M29F200BB. Datasheet pdf. Equivalent


STMicroelectronics 29F200BB
M29F200BT
M29F200BB
2 Mbit (256Kb x8 or 128Kb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA
s SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
s ACCESS TIME: 45ns
s PROGRAMMING TIME
– 8µs per Byte/Word typical
s 7 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 4 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
s TEMPORARY BLOCK UNPROTECTION
MODE
s LOW POWER CONSUMPTION
– Standby and Automatic Standby
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– M29F200BT Device Code: 00D3h
– M29F200BB Device Code: 00D4h
44
TSOP48 (N)
12 x 20mm
1
SO44 (M)
Figure 1. Logic Diagram
VCC
17
A0-A16
15
DQ0-DQ14
W DQ15A–1
M29F200BT
E M29F200BB BYTE
G RB
RP
VSS
AI02912
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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29F200BB Datasheet
Recommendation 29F200BB Datasheet
Part 29F200BB
Description M29F200BB
Feature 29F200BB; M29F200BT M29F200BB 2 Mbit (256Kb x8 or 128Kb x16, Boot Block) Single Supply Flash Memory PRELIMINAR.
Manufacture STMicroelectronics
Datasheet
Download 29F200BB Datasheet




STMicroelectronics 29F200BB
M29F200BT, M29F200BB
Figure 2A. TSOP Connections
A15 1
48 A16
A14 BYTE
A13 VSS
A12 DQ15A–1
A11 DQ7
A10 DQ14
A9 DQ6
A8 DQ13
NC DQ5
NC DQ12
W DQ4
RP 12 M29F200BT 37 VCC
NC 13 M29F200BB 36 DQ11
NC DQ3
RB DQ10
NC DQ2
NC DQ9
A7 DQ1
A6 DQ8
A5 DQ0
A4 G
A3 VSS
A2 E
A1 24
25 A0
AI02913
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE
Byte/Word Organization Select
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
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Figure 2B. SO Connections
NC
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 M29F200BT 34
12 M29F200BB 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
AI02914
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
SUMMARY DESCRIPTION
The M29F200B is a 2 Mbit (256Kb x8 or 128Kb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single 5V supply. On power-up the
memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM. The
M29F200B is fully backward compatible with the
M29F200.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.



STMicroelectronics 29F200BB
M29F200BT, M29F200BB
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature (Temperature Range Option 1)
0 to 70
°C
TA Ambient Operating Temperature (Temperature Range Option 6) –40 to 85
°C
Ambient Operating Temperature (Temperature Range Option 3)
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage
–0.6 to 6
V
VCC Supply Voltage
–0.6 to 6
V
VID Identification Voltage
–0.6 to 13.5
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
The blocks in the memory are asymmetrically ar-
ranged, see Tables 3A and 3B, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages. Access times of 45ns, 55ns,
70ns and 90ns are available. The memory is sup-
plied with all the bits erased (set to ’1’).
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A16). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
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