translating transceiver. 74AVCH8T245 Datasheet

74AVCH8T245 transceiver. Datasheet pdf. Equivalent

74AVCH8T245 Datasheet
Recommendation 74AVCH8T245 Datasheet
Part 74AVCH8T245
Description 8-bit dual supply translating transceiver
Feature 74AVCH8T245; 74AVCH8T245 8-bit dual supply translating transceiver with configurable voltage translation; 3-stat.
Manufacture NXP
Datasheet
Download 74AVCH8T245 Datasheet




NXP 74AVCH8T245
74AVCH8T245
8-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 5 — 27 December 2012
Product data sheet
1. General description
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level
translation. It features two 8-bit input-output ports (An and Bn), a direction control input
(DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)
and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are
referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on
DIR allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both An and Bn outputs are in the high-impedance OFF-state. The bus-hold
circuitry on the powered-up side always stays active.
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s (1.8 V to 3.3 V translation)
260 Mbit/s (1.1 V to 3.3 V translation)



NXP 74AVCH8T245
NXP Semiconductors
74AVCH8T245
8-bit dual supply translating transceiver; 3-state
260 Mbit/s (1.1 V to 2.5 V translation)
210 Mbit/s (1.1 V to 1.8 V translation)
150 Mbit/s (1.1 V to 1.5 V translation)
100 Mbit/s (1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVCH8T245PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74AVCH8T245BQ 40 C to +125 C
DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
4. Functional diagram
VCC(A)
B1
VCC(B)
21
B2
20
B3
19
B4
18
B5
17
B6
16
B7
15
B8
14
22
OE
2
DIR
3 4 5 6 7 8 9 10
A1 A2 A3 A4 A5 A6 A7 A8 001aai472
Fig 1. Logic symbol
74AVCH8T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 December 2012
© NXP B.V. 2012. All rights reserved.
2 of 25



NXP 74AVCH8T245
NXP Semiconductors
74AVCH8T245
8-bit dual supply translating transceiver; 3-state
DIR
OE
A1
VCC(A)
VCC(B)
B1
to other seven channels
001aai473
Fig 2. Logic diagram (one channel)
5. Pinning information
5.1 Pinning
VCC(A) 1
DIR 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
GND 11
GND 12
74AVCH8T245
24 VCC(B)
23 VCC(B)
22 OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 B8
13 GND
001aai487
Fig 3. Pin configuration TSSOP24
74AVCH8T245
terminal 1
index area
DIR 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
GND 11
GND(1)
23 VCC(B)
22 OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 B8
001aai488
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration DHVQFN24
74AVCH8T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 December 2012
© NXP B.V. 2012. All rights reserved.
3 of 25







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)